Basic Buck Converter Analog Control Circuit

Thread Starter

fzizzo21

Joined Feb 16, 2024
4
Hello, I am trying to design a 5V -> 3.3V buck converter as a design exercise and am implementing my own analog control circuit. At the moment I am not considering compensation or loop response as I am simply trying to regulate to the correct output before I consider the response and stability. Below is a photo of the control circuit, which to my understanding should be regulating to the target voltage. Note that Vfb is taken on the output from a 10k and 20k resistor divider, so should ideally be 2.178V when 3.3V is on the output. Additionally, the Vramp is a 600khz, 5V peak ramp wave. With the current loop seen below my output voltage is actually 1.27V. I am stuck at where this is going wrong and feel as though I have tried many different configurations. I have trouble thinking that a lack of compensator is causing this issue as the output is a pretty smooth 1.27V, only 2mV peak to peak.
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LowQCab

Joined Nov 6, 2012
5,101
600kHz is only going to work well in the Simulator, not so much in real-life.
Why are You wanting such a High-Frequency ?

If You don't want to directly inject ~600kHz into the Power-Rail of your 3.3-Volt Circuit,
then there must be an Output-Filter designed to eliminate it.
Without it, You do not have ~2mV of Ripple, You have 100% of extremely noisy Ripple.
The Chips being Powered by this "regulator" will probably not function,
and will probably be destroyed, without a properly designed Output-Filter.

Radio-Frequency-Circuits are notoriously squirrely and difficult to work with.

What is the Maximum-Peak-Current that will be demanded on the 3.3-Volt-Supply ?

Showing a Buffer-Amp in your Schematic doesn't convey any useful information.

There are plenty of cheap-Chips that already have all the bugs worked-out for this sort of work.
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cbelting

Joined Jan 27, 2022
2
It is difficult to say what's happening seeing only a portion of the circuit, but your mention of the feedback divider suggests some of the issue may have to do with the Thevenin equivalent of the inverting input resistance. If the feedback divider is unbuffered, the divider needs to be included when determining the amplifier's inverting gain. The omission isn't sufficient to account for all of the error but may help you focus on other contributions. While your exercise can be informative at a basic level, as LowQCab infers, this probably not the most efficient approach and appears to overlook some basic concerns seen in SMPS designs.
 
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