Biasing / designing a class A audio preamp.

Thread Starter

IcedFruits

Joined Jan 15, 2014
97
Hi, I am trying to bias the following schematic. It appears to be working, but the o/p sine wave (green) @ C2 R3 junction kinda looks odd and fat at the top side. Blue one is the i/p signal wave.



Another thing is, in many class A schematics, I find they put large value caps @ C3, but when I do so with 10uf, o/p signal really messes up.



Looking for any explanation / workaround / suggestion regarding the above, thanks. :)
 

#12

Joined Nov 30, 2010
18,224
For the first problem, you need a transistor that uses zero voltage, collector to emitter, and has no decrease in gain when saturated. They don't exist in NPN, but you might get closer with a mosfet.

For the second problem, turn down the input signal. The capacitor increases the gain of the transistor circuit and you are merely demonstrating saturation by over-driving it.
 

Thread Starter

IcedFruits

Joined Jan 15, 2014
97
For the second problem, understood, more collector current flowing. I turned down the i/p signal to 0.025v , and the o/p looks better now, although still top heavy.

And for the first issue, is there any way to make o/p more accurate while still using NPN ? Is this common to all BJT amplifiers ?
 

#12

Joined Nov 30, 2010
18,224
Is this common to all BJT amplifiers ?
Absolutely. There is no such thing as an NPN that has normal gain down to zero Vce. In fact, there is no such thing as an NPN transistor that can even GET to zero Vce. You absolutely, positively, can not produce a rail-to-rail output in that configuration.
 

Thread Starter

IcedFruits

Joined Jan 15, 2014
97
Actually I am not looking for rail to rail o/p, that I am well aware of. Just looking for a symmetrical o/p sine wave from a symmetrical i/p sine wave.
If you see the first pic, the top peak kind of looks blunt, whereas the bottom peak looks more sharp for the o/p signal.
 

Thread Starter

IcedFruits

Joined Jan 15, 2014
97
Here is the .asc file, attached.
I was wondering, if a low gain transistor will create more accurate sign wave or not, this one definitely has more area to the upper cycle, than the lower one.

Please change C3 to 1p & i/p signal amplitude to 0.2v to match my first post.
 

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crutschow

Joined Mar 14, 2008
34,048
Here's your circuit simulated with a reduced amplitude and no emitter capacitor to give some negative feedback from the emitter resistor (also called emitter degeneration).
This reduces both gain and distortion.
(There's a tradeoff between gain and distortion when you add negative feedback. You can change the value of R6 to see the change in both gain and distortion for a given output amplitude.)
There is now not an obvious difference between the positive and negative halves of the waveforms.
The transistor gain has little direct effect on open-loop distortion, but a high gain transistor will have lower distortion with a fixed gain as determined by feedback, since the more feedback (more loop gain), the lower distortion (to a first order).

upload_2016-7-8_18-22-24.png
 
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Thread Starter

IcedFruits

Joined Jan 15, 2014
97
Right, so I have played with the emitter resistance a little, and also changed the collector resistances accordingly. I appears when restrict Vce to no less than 0.6 V, it does not cause any visible distortion with 0.4V p-p i/p signal.

I measured cellphone 3.5mm o/p few days ago, it looked the o/p goes to max of 0.8v p-p. That's why, I want this circuit to accept 0.5V p-p signal without any o/p distortion, with o/p voltage swing of 2V+ @ 0.5V i/p. So, may be I am on right track ?
Any suggestion regarding the design is welcome. I will be implementing this with BC548B transistors.

 
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BobTPH

Joined Jun 5, 2013
8,665
Basically, the problem is that you cannot have the output very close to either ground or V+ without distortion.

Bob
 

dannyf

Joined Sep 13, 2015
2,197
Looking for any explanation / workaround / suggestion regarding the above, thanks.
The issue is driven by the uneven output impedance during the positive and negative cycles. During the negative cycles, the output impedance is dominated by R6 and R3 during the positive cycles.

The solution?

1) make the load much higher than R6 / R3; or
2) use a symmetrical output stage.
 

crutschow

Joined Mar 14, 2008
34,048
The issue is driven by the uneven output impedance during the positive and negative cycles. During the negative cycles, the output impedance is dominated by R6 and R3 during the positive cycles..
Not true.
The output impedance is essentially the same for both the positive and negative cycles, which is basically the parallel value of R5 and R3.
The transistor collector impedance is much higher than that (transistors act as current sources) and thus has little effect on this impedance.
R6 doesn't enter into it.

The distortion is mainly due to the non-linear (logarithmic) relation between the input base-emitter current and the base-emitter voltage.
The emitter resistor R6 serves to linearize that input voltage-current relation and thus reduce distortion.

Below is the simulation with the emitter resistor R6 bypassed, giving no feedback.
Note how the transistor base current mirrors the distortion in the collector voltage due to this base input voltage/current non-linearity.
Edit: The bottom trace shows the transistor base current with a vertical Log scale which now looks like an undistorted sinewave, indicating that the distortion is indeed due to the input log relation between current and voltage.

upload_2016-7-9_17-38-57.png
 
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Thread Starter

IcedFruits

Joined Jan 15, 2014
97
Well, thank you everybody for your help. I have built this on a veroboard, and it really increases sound quality by a lott better than nothing.

There are a few little funny effects once in a while at the high frequency region, but I will try to figure that out later.

:)
 

Thread Starter

IcedFruits

Joined Jan 15, 2014
97
thanks for the alternate approach with the base resistor, will try out the simulation.

2 questions though, how do you calculate the harmonic distortion in ltspice ?
and is that windows xp you are using ? :D
 

crutschow

Joined Mar 14, 2008
34,048
................
how do you calculate the harmonic distortion in ltspice ?
................. :D
You can do an FFT of the output signal from the View dropdown when looking at the plot window.
From that you can calculate the ratio of the harmonic amplitudes to the fundamental amplitude to get the harmonic distortion.
Run the simulation for a longer time to get better FFT resolution.
Generally the second harmonic has most of the distortion energy and the rest of the harmonics will add little to the total distortion value.
 

Bordodynov

Joined May 20, 2015
3,167
IsedFruits
I used
.FOUR -- Compute a Fourier Component after a .TRAN Analysis
Syntax: .four <frequency> [Nharmonics] [Nperiods] <data trace1> [<data trace2> ...]
Example: .four 1kHz V(out)
RUN
and see log-file (Ctrl+L).

Windows XP Professional v. 2002 Service Pack 3
 
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