What solutions exist for solving the problem of when an IC's output will be back-driven from another IC's output when both are driving the same input of a 3rd IC?


For example: I have a counter, and I want to drive the clock pin either with an oscillator, or manually with the output from a button.

I can use an AND gate or 4066 switch etc to disable the input from the oscillator but then I have the output of that IC connected to the output of my IC handling the buttons, both connected to the clock pin.

So, when I hit the button and this sends a pulse, that current will be sent into the output of the gate used for switching the oscillator signal, and vice versa, when the clock is enabled and running, and the button is not being used.


As I can see it, there are several options. First is an OR gate. I think this is the logical way, problem is, an extra gate.

Second idea I came up with was using two diodes, but I wonder if the voltage drop may be an issue.

Third (which I saw in a book) hinted at the possibility of using high value (eg: 10k+) resistors in series with the outputs to limit current, but the information was not well detailed, and I do not know if it would be OK in all cases.


Does anyone use this concept in their own designs? Are resistors suitable? Would diodes work?

Are there any other options?

 

what you look for is called MUX (short for multiplexer). it is equivalent of selector switch (SPDT)

 

I found one book (Digital Electronics Demystified by Myke Predko) that mentions the idea of using a resistor:

The book states:

"As noted in Fig. 7-4, you should only use CMOS
inverters (which are voltage, rather than current controlled) and place the
10 k resistor between the switch and the output of the left inverter. By using
this circuit, there will be no chance that the left inverter’s output is tied
directly to power or ground (which will be the opposite value that it’s at) and
the 10 k resistor will limit the amount of current that is passed. I did not put
the resistor into Fig. 7-4 as it is a basic circuit that I have seen in a number of
references and I wanted to point out that it does backdrive a gate output and
there are ways of avoiding this problem."

But there is no solid evidence that this solution would be suitable in other scenarios, such as mine.

 

I have never heard of the expression "back-driving" before.
I have to assume that you are attempting to perform some logic function, either an AND or OR logic function.
Use a logic gate to do this.

 

What solutions exist for solving the problem of when an IC's output will be back-driven from another IC's output when both are driving the same input of a 3rd IC?

...

Are there any other options?

Here "backdriving" means driving a voltage into the output of a device. Generally that's a very bad thing so you need to handle it in some special manor.

Consider the above Fig 7.4: without the switch the inverters form a flip flop: assume any state on either input and you will see that is a stable pattern. The trick is to be able to change this, so by adding the 10K resistor the output is protected when we use a switch to force a 1 or a 0 on the right side input.

Now back to the original question of the counter clocked off either an oscillator or a button: just how to do that depends on what is desired. How fast is the oscillator? Does using the button stop the oscillator from working or just add some extra pulses?

Ultimately, does pressing the button advance the count on the press or the release?

A simple resistor such as described in the fig will not work... the button locks the output to either high or low so the osc will not clock the circuit.

Note this debounce circuit is a possible candidate to correct the button as a counter *will* count every bounce and glitch on it's clock line.

Now if the oscillator is slow (once a sec or less) you may be able to combine the osc output and the debounced button with an exclusive or gate. Such a gate will make the clock line clock (go both hi and low) when the button is pressed & released no matter if the oscillator signal is hi or low at the time.

 

The circuit shown in Fig. 7-4 is a flip-flop used as a switch debouncer.
There is nothing wrong with doing this without the resistor.

When the switch is either GND or Vcc, opposing the output of the gate, the flip-flop will switch instantaneously (within two propagation delays, under 10ns) and presents no harm to the output gate.

 

OK here's a quick example I worked up to show what I am thinking of.

There would of course be other circuitry to allow only the clock or the button to be active at any time, not both.

Assume the button is debounced already.

Option 1 is obviously the logical choice but Option 2 saves space and another IC. Going from what I read in Don Lancaster's 'CMOS Cookbook' it should work OK.

Based off the concept as I showed earlier from the book mentioned previously, I came up with Option 3. I have no idea as to its feasibility, which is why I am asking.

No where have I seen such an idea shown explicitly but the concept seems similar to that in Figure 7-4, which is apparently OK to use.

 

You can avoid using any additional components by using a 74HC126 tri-state buffer gate or similar.

 

A 74HC126 could work theoretically but my design will be running from 12v so I don't think it will actually be possible to use it. I forgot to change the supply voltages in my examples.

The more I look at Option 3 the more it looks wrong. I don't know anyone that uses it but I am still intrigued as to its feasibility.

If the current can be limited safely in figure 7-4 with a resistor, what is wrong with the concept of Option 3, which as I see uses the same principle? There must be a reason why it's not written anywhere.

 

In that case, there are many other CMOS solutions:

4016 - Quad bilateral switch
4066 - Quad analog switch
4019 - Quad AND/OR select gate
4048 - Multifunction expandable 8-input gate
4503 - Hex non-inverting tri-state buffer

 

#1 will of course work just fine, as will #2. #3 is a problem as when U5A goes hi and U5B goes low you are driving the next gate with a logical 0.5 (half VDD) (oops, a bad thing).

#2 works with CMOS, not so good with TTL unless you get picky with the resistor value.

Common to all these techniques is the problem when you switch input types you may get a count just from that itself. The clock of the 4516BT triggers on rising edge of the clock. Say you just switch from button to 1Hz clock, and the clock happens to be high: as soon as you switch sources the counter counts by 1, which may not matter here but something to keep in mind for that one day when that extra count is important.

Your schematic sketches are very good. A good schematic is a great starting point!

 

The circuit shown in Fig. 7-4 is a flip-flop used as a switch debouncer.
There is nothing wrong with doing this without the resistor.

When the switch is either GND or Vcc, opposing the output of the gate, the flip-flop will switch instantaneously (within two propagation delays, under 10ns) and presents no harm to the output gate.

Which of course means the output of the gate WILL be shorted for a minimum of two propagation delays either sinking or sourcing an uncontrolled amount of current each and every time the button is pressed and released.

This is not recommended for any design. It's just a poor practice.

 

The most you are going to get out of a shorted output of a CMOS 4069 inverter at 15V is 6.8mA.

 

#1 will of course work just fine, as will #2. #3 is a problem as when U5A goes hi and U5B goes low you are driving the next gate with a logical 0.5 (half VDD) (oops, a bad thing).

It was bugging me there was something wrong with it, of course, when the gates are different values it's a voltage divider! Don't know why I didn't see that before... So, while the resistors would probably limit the current to a safe level, it still wouldn't work because the output voltage level would be useless.

Common to all these techniques is the problem when you switch input types you may get a count just from that itself. The clock of the 4516BT triggers on rising edge of the clock. Say you just switch from button to 1Hz clock, and the clock happens to be high: as soon as you switch sources the counter counts by 1, which may not matter here but something to keep in mind for that one day when that extra count is important.

When I switch from the button to the clock, The extra count shouldn't be an issue as I want it to start counting then. I think though the pulse then may come sooner than normal so the counter may advance the first two counts in less time than any subsequent two counts - is this what you're saying? If this turned out to be a big problem, would it be possible to stop the first pulse somehow?

Your schematic sketches are very good. A good schematic is a great starting point!

I hope so I'm not new to drawing them up, only new to designing circuits myself.

 

If this turned out to be a big problem, would it be possible to stop the first pulse somehow?

Oh yeah, probably lots of ways. Off the top of my head one could make the switch input only change states when the clock goes high, thus only allowing a change when it should next happen. A flip flop driven by the same clock would do this.

Probably several other ways (some simpler) to do it too.

 

you need to specify functionality exactly, only then working circuit can be created. you keep mixing analog and digital to accomplish digital functionality. why hack when you can have proper design? just state your requirements clearly, draw timing diagram and then we can help. basic mux can be created using NAND gates such as 4011B. selection button/clock is done via one input. this will work on 12V too (up to 15 or 18V for B seriei CMOS).