Any suggestion to interface between different logic levels? (0-5V to -2.5-2.5V)

Thread Starter

btondin

Joined Apr 27, 2013
7
Hello,

I'm designing a circuit that generate analog EMG (eletromyography) signals from a dataset. My circuit uses and D/A converter (DAC8831) with digital levels: Vss = 0V and Vdd = 5V but the analog output is -2.5V and 2.5V centered in 0V (the same 0V of digital Low). In the sequence I have a SPI controlled PGA (MPC6S21) with the digital levels: Vss = -2.5V and Vdd = 2.5V, and the analog input and output: -2.5V to 2.5V centered in 0V. My question is: since the logic level LOW of my circuit is 0V and HIGH is 5V. There is an easy, low component count and low power way to level translate the LOW level to -2.5V and HIGH to 2.5V? I know that i can do that using 3 ampop (for CS, SCK and SI) in open loop fed with -2.5-2.5V with the IN- attached to 2.5v and IN+ receiving voltage divided signal (0 to 2.7V per exemple). But this method seems "bulky" and overdsigned. It must handle SCLK of 10MHz minimum.

(Schematics Attached)

Thanks!!!
 

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WBahn

Joined Mar 31, 2012
26,398
Could you supply a link to the data sheets of the parts you are using, particularly the MPC6S21?

Is there a reason you can't run everything off the same 5 V span of power? In other words, is there anything special about where "o V" gets parked?

You say that your minimum clock speed is 10 MHz. What is your maximum clock speed?
 

Thread Starter

btondin

Joined Apr 27, 2013
7
Could you supply a link to the data sheets of the parts you are using, particularly the MPC6S21?

Is there a reason you can't run everything off the same 5 V span of power? In other words, is there anything special about where "o V" gets parked?

You say that your minimum clock speed is 10 MHz. What is your maximum clock speed?
I wrote wrong the name of the PGA. is MCP6s21 (http://ww1.microchip.com/downloads/en/DeviceDoc/21117B.pdf)

If i change my voltage reference i'll face other problems, so i'll stick with just find a solution for the "level convertion" problem.

My SPI clock speed is 10MHz, so the solution will have to deal with this frequency, no less. Using optocouplers would not be a good choice, for instance.

I found two solutions: the easyest way is using an isolator like the ISO family of Texas instruments or ADUM of Analog Devices. The cheap way is using some BJTs and resistors, but it inverts the logic signals. Not a huge problem
 

daz E

Joined Nov 7, 2017
47
Capture.PNG Capture.PNG

EDIT: apologies, first diagram downshifts 5 to 2.5 system , 1K should be 10K - my bad

2nd diagram from datasheet , upshifts 2.5 to 5V logic Vref would be from your +5V Vcc, dividing this with 2x10K to 2.5V.

Many, many ICs do the same thing - google is your friend.
 
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