Hello,
I'm designing a circuit that generate analog EMG (eletromyography) signals from a dataset. My circuit uses and D/A converter (DAC8831) with digital levels: Vss = 0V and Vdd = 5V but the analog output is -2.5V and 2.5V centered in 0V (the same 0V of digital Low). In the sequence I have a SPI controlled PGA (MPC6S21) with the digital levels: Vss = -2.5V and Vdd = 2.5V, and the analog input and output: -2.5V to 2.5V centered in 0V. My question is: since the logic level LOW of my circuit is 0V and HIGH is 5V. There is an easy, low component count and low power way to level translate the LOW level to -2.5V and HIGH to 2.5V? I know that i can do that using 3 ampop (for CS, SCK and SI) in open loop fed with -2.5-2.5V with the IN- attached to 2.5v and IN+ receiving voltage divided signal (0 to 2.7V per exemple). But this method seems "bulky" and overdsigned. It must handle SCLK of 10MHz minimum.
(Schematics Attached)
Thanks!!!
I'm designing a circuit that generate analog EMG (eletromyography) signals from a dataset. My circuit uses and D/A converter (DAC8831) with digital levels: Vss = 0V and Vdd = 5V but the analog output is -2.5V and 2.5V centered in 0V (the same 0V of digital Low). In the sequence I have a SPI controlled PGA (MPC6S21) with the digital levels: Vss = -2.5V and Vdd = 2.5V, and the analog input and output: -2.5V to 2.5V centered in 0V. My question is: since the logic level LOW of my circuit is 0V and HIGH is 5V. There is an easy, low component count and low power way to level translate the LOW level to -2.5V and HIGH to 2.5V? I know that i can do that using 3 ampop (for CS, SCK and SI) in open loop fed with -2.5-2.5V with the IN- attached to 2.5v and IN+ receiving voltage divided signal (0 to 2.7V per exemple). But this method seems "bulky" and overdsigned. It must handle SCLK of 10MHz minimum.
(Schematics Attached)
Thanks!!!
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