Analyzing a CMOS NAND gate

Thread Starter


Joined Mar 16, 2016
Hi everyone,

My textbook has an example NAND gate:
Screenshot from 2016-04-06 15-25-01.png
and it says the following:
When A = 1 and B = 0,
N1 is ON, but N2 is OFF, blocking the path from Y to GND.
P1 is OFF, but P2 is ON, creating a path from Vdd to Y.
Therefore, Y is pulled up to 1.
The problem is that I can't figure out why P2 is ON. To me both P1 and P2 are connected directly to A so they should both be OFF.

Can you tell me what's wrong with my reasoning?