Hi everybody,

I am new here and I would like some help to design an opamp for my D/A converter. I would like to design with cmos transistors a R-2R architecture converter. I did it with a model of opamp, but now I need to design the opamp with cmos. And I do not know how to do. Could you help me ?
I thank you...

bye

 

Is this a college course that you are currently taking? What other circuit elements have you designed?

An opamp typically requires multiple circuit elements put together to get the overall desired result. You will typically need three stages. 1) a differential input stage, 2) an inverting stage, and 3) an output stage. Also, when you are designing in CMOS you will need to set up a reference current source to be used across the design.

 

Hi,
Thank you for your answer... It is for a Master's course.
I show you what I did, but currently, it does not work..
Do you know why by looking at my design?

 

Just a couple of quick questions:

1) How are you biasing the inputs to the op amp? From the R-network page it looks like the bias is around GND. The op amp lower supply also seems to be GND which would probably never turn on M4. INP needs to be higher than TEST0 to turn it on. Is that what you are seeing in the simulations? You may need to add a -Vcc supply or bias the input at 0.5 Vcc. If you bias at half supply you have to make sure your R network does the same thing.

2) Are you going to need an output stage? The 1 kohm feedback resistor may affect the output and frequency response of the circuit.

 

As StayatHomeElectronics implied, your op amp's input common mode range does not include the negative rail (ground). There are designs for rail-to-rail I/O op amps, but they are much more complex. If you want to run your inputs at ground, you will need a negative supply.

What is the value of R in your R-2R ladder?

EDIT: if you change all the N-channels to P-channels and vice-versa (only in the op amp), your input common mode range can include ground.

 

You are right, my inputs are biased like this:
INN = signal from the R-2R ladder
INP = gnd
My supply voltages for the whole circuit are Vss=0V VDD=5V and I am not supposed to use a negative one.
The value of R is 1kohm

I tried to bias at 2.5V the INP input as you suggested to me, but the signal was worse.
I need the feedback resistor to convert the current into voltage. Is it what you call "output stage"?

I did a changement in the R-2R ladder switch. Instead of using pMos, I used nMos with an inverter before. Because I noticed that their resistances were not equal and so I did not have a symmetrical current through the transistors. Now I have a symmetrical current through them, but the behaviour of the converter remains incorrect.
I think it could be due to the opamp which may be not adapted. But I do not know what I can change on it....

 

An output stage is used to give you low output impedance so that anything you use as a load will not affect the operation of the circuit.

What do you mean by the signal is worse? How are you testing the circuit?

 

I test the circuit bit after bit. So when bit0=1 I expected to have V=VDD/(2^8)=19mV ... when bit7=1 -> V=VDD/(2^1)=2.5V
But I do not obtain these values, what I obtain has no sense..

How can I do an output stage? I thought to do it in the opamp..

 

The output stage is definitely part of the op amp.

 

Do you get good bias conditions when INN and INP are the same?

Are the MOSFETs with the arrow n-channel and the ones with out the p-channel?

Are you getting a good I(bias)?

 

Did you see my previous edit?

If you change all the N-channels to P-channels and vice-versa (only in the op amp), your input common mode range can include ground.

 

Hi,
First, Ron H I saw your advice and I tried it. You can see the results on the image, it is not satisfying.

Then, The mosfets with the "arrow" (it is the ground connected to the bulk) are the n-channel, and the other ones are the p-channel.
Sizes in um:
N-Mos:
M1=M4 -> 7.6/0.5 parallel device=1
M5 -> 7.6/0.5 parallel device=1
M6 -> 7.6/0.5 parallel device=2
M8 -> 7.6/0.5 parallel device=6
P-Mos:
M2=M3 -> 12.4/0.55 parallel device=2
M7 -> 24.8/1.1 parallel device=10
M9 -> 0.55/12.4 parallel device=3

The current I get is constant : I (M5) = 14u , I (M6) = 34u and I (M8) = 116u.
Have a look at the image "converter", you can see Vout when INN=INP

I really do not know why it does not work...Do you have some other ideas to design a DAC with its opamp?

 

You may not have enough current in the differential stage to bias it correctly.

Break it down and test each part of the amplifier separately. Make sure the differential portion is working before moving on to the next part.

 

Hi,
First, Ron H I saw your advice and I tried it. You can see the results on the image, it is not satisfying.

Then, The mosfets with the "arrow" (it is the ground connected to the bulk) are the n-channel, and the other ones are the p-channel.
Sizes in um:
N-Mos:
M1=M4 -> 7.6/0.5 parallel device=1
M5 -> 7.6/0.5 parallel device=1
M6 -> 7.6/0.5 parallel device=2
M8 -> 7.6/0.5 parallel device=6
P-Mos:
M2=M3 -> 12.4/0.55 parallel device=2
M7 -> 24.8/1.1 parallel device=10
M9 -> 0.55/12.4 parallel device=3

The current I get is constant : I (M5) = 14u , I (M6) = 34u and I (M8) = 116u.
Have a look at the image "converter", you can see Vout when INN=INP

I really do not know why it does not work...Do you have some other ideas to design a DAC with its opamp?

View attachment 8903

View attachment 8904

I didn't think it was necessary to tell you that you also need to swap the power supplies. I thought a master's student would know this.

 

I saw my mistake too late... I am stupid..
I started electronics this year, I do not have the reflex yet..

thank you for your help, I will continue my investigations in order to get a correct circuit which will work well!