For the ALS logic circuit shown, estimate:
(a) the current IOL
(b) the delay in a 1-to-0 transition at one of the inputs of GATE 1
appearing as an effect at the output of GATE 5.
(c) the total power consumed by the circuit in a quiescent state.
I think this a NAND gate logic circuit, in red I have added the inputs and outputs. I have 2 tables that show typical values of certain logic families. For (a) the low level output according to the table is 4mA for ALS, the low level inputs for gates 2,3 and 4 are 100uA each. Never been asked to estimate these things before although I have heard that it is simple addition.


(a) the current IOL
(b) the delay in a 1-to-0 transition at one of the inputs of GATE 1
appearing as an effect at the output of GATE 5.
(c) the total power consumed by the circuit in a quiescent state.
I think this a NAND gate logic circuit, in red I have added the inputs and outputs. I have 2 tables that show typical values of certain logic families. For (a) the low level output according to the table is 4mA for ALS, the low level inputs for gates 2,3 and 4 are 100uA each. Never been asked to estimate these things before although I have heard that it is simple addition.

