I agree with Irving. He has the right idea.
In my case, using GAN-MOSFETS I have to go beyond. You don't need to do what I say, this is just to show an example.
I get the next bigger caps for C1,C3 so I can get a wide trace out through the caps. (if needed)
I put the Gate driver on the right side, so the Gate-Out pin is "looking" right at the Gare of the MOSFET.
I try hard to not have VIAs in the Gate, and Gate return path. VIA adds a little inductance. (at 100khz it probably does not matter)
The loop of Gate-Driver to MOSFET and back to the IC needs to be small. A loop of wire makes an inductor. Try to make the diameter of the loop as small as you can.

 

I like the way this schematic is drawn. The high current nets are drawn wide. There are comments.
Sometimes I hire the layout done. I am not there to make every choice. So, I have net names like (1200V 36A) This helps in laying out the board. Most people never change the line width in a schematic, and most people never change the color. I use color and line width as a reminder of how-to layout the board.
In most CAD systems there are layers that are not normally seen. (normally turned off) I put comments all over the schematic. Sometimes in a normal layer and sometime in a not seen layer.
The math you did to design the L1 is complicated and will be lost soon. Put that on a hidden layer or even a new page. Next year when you have to make a change it will be easy.
You can say " 80N60 is a good part but the 80N100 also works". and "Don't use the part xxxxx, it broke in testing".
I like that 25V - 42V is at the top of the schematic and GND is at the bottom. Too many people put the supply at the bottom.

Good job!

 

I like the way this schematic is drawn. The high current nets are drawn wide. There are comments.
Sometimes I hire the layout done. I am not there to make every choice. So, I have net names like (1200V 36A) This helps in laying out the board. Most people never change the line width in a schematic, and most people never change the color. I use color and line width as a reminder of how-to layout the board.
In most CAD systems there are layers that are not normally seen. (normally turned off) I put comments all over the schematic. Sometimes in a normal layer and sometime in a not seen layer.
The math you did to design the L1 is complicated and will be lost soon. Put that on a hidden layer or even a new page. Next year when you have to make a change it will be easy.
You can say " 80N60 is a good part but the 80N100 also works". and "Don't use the part xxxxx, it broke in testing".
I like that 25V - 42V is at the top of the schematic and GND is at the bottom. Too many people put the supply at the bottom.
Good job!

Sorry for the delayed response.
I actually follow a very similar approach. All key cautions, layout guidelines, and design rules are documented in a design log, including detailed calculations such as the L1 design. This helps preserve the reasoning for future revisions and makes handoff to layout or later debugging much easier.

 

OK. I think there are multiple issues with this board.

You need some bulk capacitance on VDDB as per VDDA. VDDA needs a small eg 100n capacitor alongside the 10u, as per datasheet. Consider changing the 1N4148 for a schottky or fast-recovery device.

The gate traces should ideally be of similar length and much shorter and thicker. That long thin (0.25mm) trace from VOC is about 100-130nH of inductance, the short one about 30-50nH. Making them as thick as possible will help reduce ringing. Similarly the traces from the driver GNDA pin to their respective VOX_Y_GND traces need to be of a similar width.

The gate traces also run parallel to the VOA_B_GND and VOC_D_GND which have 10A transients. This is going to induce some undesired voltage into the gate traces, possibly sufficient to partially turn on a MOSFET that should be off. Ideally the drivers should be below the MOSFETs so the gate traces run at right angles to the power lines. Alternately use a 4-layer board with an internal ground plane.

Here's a sanitized snippet of one I did a while back using similar devices:

Apologies for the delayed response.
Thank you so much for the time and effort you’ve put into reviewing the board. Your detailed observations are extremely helpful, and the sanitized snippet you shared gave us much more clarity especially on the gate routing and grounding approach. I truly appreciate you taking the effort to explain this so clearly.

 

I agree with Irving. He has the right idea.
In my case, using GAN-MOSFETS I have to go beyond. You don't need to do what I say, this is just to show an example.
I get the next bigger caps for C1,C3 so I can get a wide trace out through the caps. (if needed)
I put the Gate driver on the right side, so the Gate-Out pin is "looking" right at the Gare of the MOSFET.
I try hard to not have VIAs in the Gate, and Gate return path. VIA adds a little inductance. (at 100khz it probably does not matter)
The loop of Gate-Driver to MOSFET and back to the IC needs to be small. A loop of wire makes an inductor. Try to make the diameter of the loop as small as you can.

Since we are planning to move toward GaN MOSFETs in our upcoming designs, could you please highlight the critical considerations we should be mindful of particularly with respect to gate-driver placement, minimizing gate and return-path loop inductance, via usage in sensitive paths, component placement around the power and gate loops, and any layout or protection practices that become especially important for GaN devices compared to silicon MOSFETs?

 

we are planning to move toward GaN MOSFETs

link Here is a part that I love and hate. lol
There are many different type of GaNs. Working with them is like microwave.
The gates require a very small voltage.
Most MOSFETs I drive with 10,15 or 18V of gate drive and OFF=0V.
With most GaNs 5V is max. (breakdown voltage) On this part I have the on voltage=4V.
While the data sheet shows OFF=0V I do not do that. I had better results with -1V.
I have a very good scope, and still, I really can't see Gate ringing, but I know it is there by watching the Drain current.
When I adjust the off voltage from 0V to -4V the heat loss suggests there must be about 1V of ring, or enough to almost turn the transistor back on. At -1V and below the losses were better.

Use a GaN Gate Driver. Look at the layout in the data sheet. Maybe later I can take pictures of some of my boards.
I fought for every mm of distance. My Gate Resistor touches the Gate lead and the Gare Driver IC.
There are Gate Driver Demo boards. Look at their layout.

 

1. Those gate traces are very thin. They need to be wider for low inductance. Also, each source return should be under each gate trace so that it is a low-impedance transmission line. That teeny trace with no source return under it creates a huge inductance.
2. The gate driver output will fail if the output voltage is pulled more than 0.5V below the return pins. These types of driver IC need a Schottky diode from each output to its return. I've been in touch with TI field engineers. They don't seem to know that MOSFETs and traces have inductance that will cause this.
3. Why a 600V MOSFET for a 42V circuit?

 

1. Those gate traces are very thin. They need to be wider for low inductance. Also, each source return should be under each gate trace so that it is a low-impedance transmission line. That teeny trace with no source return under it creates a huge inductance.
2. The gate driver output will fail if the output voltage is pulled more than 0.5V below the return pins. These types of driver IC need a Schottky diode from each output to its return. I've been in touch with TI field engineers. They don't seem to know that MOSFETs and traces have inductance that will cause this.
3. Why a 600V MOSFET for a 42V circuit?

Thank you for reviewing the design and for the valuable feedback.
The 600 V MOSFET was selected intentionally, as this is an early prototype. In a future iteration, we plan to increase the input voltage; the current 42 V operation is only for initial validation.
Could you please elaborate on your point about the gate driver output failing if the output is pulled more than 0.5 V below the return pin? We’d like to better understand the failure mechanism and any layout or protection recommendations you suggest.

 

link Here is a part that I love and hate. lol
There are many different type of GaNs. Working with them is like microwave.
The gates require a very small voltage.
Most MOSFETs I drive with 10,15 or 18V of gate drive and OFF=0V.
With most GaNs 5V is max. (breakdown voltage) On this part I have the on voltage=4V.
While the data sheet shows OFF=0V I do not do that. I had better results with -1V.
I have a very good scope, and still, I really can't see Gate ringing, but I know it is there by watching the Drain current.
When I adjust the off voltage from 0V to -4V the heat loss suggests there must be about 1V of ring, or enough to almost turn the transistor back on. At -1V and below the losses were better.

Use a GaN Gate Driver. Look at the layout in the data sheet. Maybe later I can take pictures of some of my boards.
I fought for every mm of distance. My Gate Resistor touches the Gate lead and the Gare Driver IC.
There are Gate Driver Demo boards. Look at their layout.

Your point about GaN gate sensitivity and using a small negative off-voltage makes sense. We’re currently driving the gate with 0 V off, but your observation about residual ringing showing up as drain current (and heat) is a good insight. We’ll definitely look into that. Appreciate you sharing this practical perspective.

 

Could you please elaborate on your point about the gate driver output failing if the output is pulled more than 0.5 V below the return pin?

The output can be pulled below -0.5V due to the ringing at the gate, when the trace inductance is large and there is a large reverse recovery current in the FETs. You wrote that you saw failures even when the FETs were not installed so, this may not be the case.
Also, we all agree that the delay between A–B and C–D is critical but, what is that delay from your control circuit?

 

Also, we all agree that the delay between A–B and C–D is critical but, what is that delay from your control circuit?

Yes that delay is being set by the control circuit.

The output can be pulled below -0.5V due to the ringing at the gate, when the trace inductance is large and there is a large reverse recovery current in the FETs. You wrote that you saw failures even when the FETs were not installed so, this may not be the case.

could the bootstrap circuit be contributing to this behavior in any way? Additionally, we observe an initial current spike of about 16 mA to 30 mA when the isolated gate driver supply is first turned on. What are your thoughts on whether this startup behavior could be related to the observed issue?

 

You have two 1N4148 diodes. Are you certain they are 1N4148? You must have a fast diode there.
I think you added a resistor.

 

You have two 1N4148 diodes. Are you certain they are 1N4148? You must have a fast diode there.
I think you added a resistor.

You mentioned the two diodes being 1N4148. Just to clarify, those have already been changed to Schottky diodes in the l testing.

 

Can you replicate the damage even without the mosfets?
If yes then its probably cause of some over voltage on the rails or excessive current from the bootstrap circuit.
If no:
1. is there a negative voltage between VOA and GNDA? measure with high frequency bandwidth.
2. what is the gate resistor? if it is too small there could be over-current in the driver which causes it to fail (either because of excessive junction temperature or by excessive bond-wire current)

 

Can you replicate the damage even without the mosfets?
If yes then its probably cause of some over voltage on the rails or excessive current from the bootstrap circuit.

What conditions would cause the bootstrap circuit to exhibit this behavior?
In particular, could power-up or supply sequencing, turn-on of the isolated gate-driver supply, excessive bootstrap capacitance, long high-side on-time, or high dv/dt transients lead to over-voltage on the rails or excessive current drawn by the bootstrap path?