6 Transistor SRAM functioning as compute SRAM and its operation.

This is the transistor level diagram of a 6 transistor SRAM, where two SRAM cell in column uses the same bitlines (BL/BL'). Each cells containing a single binary bit (say A and B). Cell A and B are activated through WL_A and WL_B signals during functioning, here it is logic computation on bitlines. Can you verify the truth table given,

how when A=0, B=0 :
VBL is discharging, but the logic at BL is showing 1,
VBL' is VDD, but logic in table is 0.

similarly for last row also.
how BL = (AB)' and BL' = A+B
Any explanation for such logic, i got this from a research paper.