Obviously U8 (top circuit), U5 (bottom circuit) won't work as configured.
What is that op amp circuit supposed to do (follower?) ?

 

I was referencing mostly U9 and U10. "Low pass filter" is not even close to a DETAILED explanation. Nor is "comparator for PSK"
The only purpose fora detailed explanation is to bring out the error that is causing the problem. It is a standard approach for bringing out errors.

 

It's got to be a really low frequency FM signal it if can get through a 741!

Nope. All of the opamps in post #7 are running at unity gain. Depending on the datasheet, a 741 GBW ranges from 0.5 to 1.5 MHz.

A bit noisy, maybe, but flat to 20 kHz with lotsa room to spare.

ak

 

I tried to replicate the exact circuit from the manual. Here is a description from the same manual:

For the FM demodulator:

Frequency demodulation, also called discriminator, converts a frequency signal into a linear voltage signal. Generally, FM-to-AM converters, balanced discriminators, phase-shift discriminators, and phase-locked loops (PLLs) are used for frequency demodulation. This chapter will describe demodulation using phase-locked loops.
A phase-locked loop (PLL) is a type of feedback circuit where, in a feedback loop, the feedback signal is locked to the frequency and phase of the output signal, providing the same frequency and phase as the input signal. In wireless communication, the carrier signal frequency is maintained. Changes occur due to transmission by the PLL in the receiver, which acts to lock the carrier signal. In this experiment, two types of PLLs will be used: the first type is used as a demodulator to separate frequency-modulated signals, and the second type is used to lock the carrier signal when the carrier signal frequency is changed to match the source signal.
A typical phase-locked loop consists of three components:
1. Phase Detector (PD)
2. Low-pass filter (LPF)
3. Voltage Controlled Oscillator (VCO)
The PLL structure is shown in Figure 5-3. The input signal and the VCO signal are sent to the phase detector for comparison and to generate an output signal in the form of a pulse. This pulse is then sent to the low-pass filter to remove unwanted signals and DC voltage. The frequency of the output signal is controlled by the DC voltage signal, as shown in Figure 5-3.

For the FSK:

In digital communication systems, FSK modulation is used to convert the voltage level of a digital signal into frequency for transmission over long distances. Therefore, to receive the signal, it must be decoded to obtain the digital signal back, which means converting the frequency back to voltage. A phase-locked loop (PLL) is used to demodulate this signal. A phase-locked loop can detect the input signal frequency and phase. PLLs are commonly applied in wireless communication systems, similar to AM or FM modulators or frequency selectors. In digital communication systems, there are digital PLLs that operate synchronously. A phase-locked loop consists of three parts: a phase detector, a loop filter, and a voltage-controlled oscillator (VCO), as shown in Figure 5-3. The operating principle of... The phase-locked loop (PSL) operates as described in the previous section. Therefore, as shown in Figure 5-3, when the frequency signal changes, the output signal of the phase detector also changes, as does the voltage level of the output signal.
This principle can be applied to construct an FSK demodulation circuit. By inputting FSK signals with frequencies f1 and f2 to the inputs of the circuit in Figure 5-9, the frequency signal f1 is converted into a voltage signal V1, and similarly, the signal f2 is converted into V2. When these voltage signals pass through a comparator with a reference voltage between V1 and V2, a digital output signal is obtained from the comparator. This entire process constitutes FSK demodulation.

This experiment involves constructing an FSK demodulator using a 74HC4046 PLL, with the circuit shown. This circuit comprises a phase detector, a frequency control voltage, and a phase detector with a charge pump circuit. Pin 10 of the 74HC4046 is connected to resistor R4, a variable resistor VR2, and a comparator constructed from an op-amp to obtain a TTL signal. The reference voltage of the comparator can be adjusted by adjusting the resistor VR2.

 

OK, I see my serious error!! For an example of what I meant when I suggested a DETAILED Description of the circuit operation, See some of the articles written by BOB PEASE, that include descriptions of how a circuit functions. Mister Pease was one of those folks whose understanding and insights were very good.

 

Note that the 564, 565, and 567 also have voltage-controlled oscillators, although maybe not as user-friendly as the 566.

ak