3T DRAM design in Cadence

Discussion in 'Digital Circuit Design' started by 8051HELP, Oct 22, 2016.

  1. 8051HELP

    Thread Starter New Member

    Nov 27, 2015
    5
    1
    Hi.

    My question is:

    Why High value of signal OUT drop down when signal for read information is logical "1".
    The signal OUT drop for about 0.7 V. That is case when is treshold voltage lower (bulk and sours is connected together -mosfet with line of information and write line)-that we need to get higher value of OUT (logical 1).

    When I use normal shematic without connecting bulk and sours , OUT signal is not sensitive when is read signal is active.
     
  2. dl324

    AAC Fanatic!

    Mar 30, 2015
    8,518
    2,047
    Post a schematic of the circuit so we can better understand what you're talking about.
     
  3. 8051HELP

    Thread Starter New Member

    Nov 27, 2015
    5
    1
    BL read is OUT signal
     
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