3T DRAM design in Cadence

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Joined Nov 27, 2015

My question is:

Why High value of signal OUT drop down when signal for read information is logical "1".
The signal OUT drop for about 0.7 V. That is case when is treshold voltage lower (bulk and sours is connected together -mosfet with line of information and write line)-that we need to get higher value of OUT (logical 1).

When I use normal shematic without connecting bulk and sours , OUT signal is not sensitive when is read signal is active.