For educational purposes I would like to create a circuit that refreshes the DRAM. As a principle I think I know how it works; at regular intervals all the bytes are read and "rewritten" to prevent the capacitors from losing their charge.
But in practice how is it made?

Do you have practical or even principled schemes that show how it works?

 

https://en.wikipedia.org/wiki/Memory_refresh

Every read is destructive, so every time a memory address is read, it must be refreshed.

The idea is pretty trivial -- you read the data and store it in a set of buffers and then turn around and write the contents of the buffers back into the address you just read.

 

IIRC the periodic refresh can work on an entire row. This is referred to as RAS-only refresh. It seems to me that all rows had to be refreshed every 2 ms. (DRAMS from ca. 1970-1985). I have not had any occasion to use DRAMS in the modern era from 1985 to the present.

 

For educational purposes I would like to create a circuit that refreshes the DRAM. As a principle I think I know how it works; at regular intervals all the bytes are read and "rewritten" to prevent the capacitors from losing their charge.

You don't have to refresh all cells at once. Doing that would block access to the DRAM more than is necessary.

Refresh is done a row at a time, but some chips accessed two rows at once. As I recall, refresh was once required every 4ms, then 2ms, then further reduced to the microsecond range as densities got higher.

Some chips had internal row counters that enabled CAS#-BEFORE-RAS# REFRESH cycles without external row addresses needing to be provided.

To give more appropriate information, we need to know what type of DRAM you want to refresh.