Floating output are almost always acceptable, so Q4-Q9 can be left unconnected. It is floating inputs that can cause erratic circuit operation and component failure.

I believe you have to do a power calculation and you will see that it's under the power limit of the LED in the buffered cases.

The power dissipated by the LED is not the immediate issue. CMOS output transistors, even the more beefy "B" series parts, are not designed to drive much of anything except other CMOS inputs. That your parts have survived is due more to luck than physics. never include design margin in good design practice.

An exception is the "AC" series, which can source and sink 24 mA (but not all outputs simultaneously, and there still is a significant output voltage drop).

ak

 

Ok I’m listening to you guys. You have more experience than I do. Appreciate the discourse. How do you size the resistor? Is there a recommended size or calculation?

 

A CMOS output voltage varies with the output current; it is not as "stiff" as a true voltage source such as a power supply output. Still, you can treat it as such to start. Assume a positive output voltage driving an LED connected to GND:

Start with the amount of current you want through the LED.
Subtract the LED forward voltage Vf from the Chip power supply voltage.
Use Ohm's Law with the remaining voltage and the LED current to calc the resistor.

However ...

This assumes that the LED current is less than the rated output current of the device. If so, then there might be a table or chart to show how the output voltage varies with output current. Use this to approximate the output voltage and calc the resistor.

ak

 

start with safe... then get it where you want... got it. Here you guys are popping my balloon... I thought these things were built like tanks! In fact the high heat seems to occur when both P and N mosfets are on at the same time and also from the transition. The current mirror seems to do a good job of keeping the chip safe. I've never run more than a few LED's on the outputs. I might have to do some destructive testing. I have some extra chips I can spare.

It says in the buffered output datasheet that the buffered output has an impedance of 400 ohms. Could that be what's protecting the chip and reducing current?

 

Yes, but relying on the channel resistance is not good practice. For one thing, it varies significantly with temperature.

ak

 

Thanks for explanation. I'm paying more attention and obviously anyone can post whatever they want on the internet. The more credible designs add 150-470 ohms resistance on LED even for 5V VCC, There are so many examples where this isn't done I thought this was one of those cool features of these chips.

Actually still looking and it's really half and half... it appears that if you want to save some of the 6-10mA output through LED you place resistor in series... otherwise so many textbook examples of just going straight to LED and ground.

If the output impedance is affected by heat then you are implying that it could have an avalanche effect.... hmmm

 

OK, in the absence of any direction from the TS, I have arbitrarily proclaimed that the first LED stage has fewer LEDs than the other stages, and can get by with only one driver transistor. This frees up one to act as the inverter for the Reset signal, eliminating Q1.

I'm happy now.

ak

 

Think the OP will come back?
Compacted 4017 version of stacker- stack one output on top of another to make a bar graph.
I see that that I reversed LED arrangement but it is just an exercise in futility anyway.
I think I would use a shift register, like 74C164.

 

If the output impedance is affected by heat then you are implying that it could have an avalanche effect.

No, I'm not.

 

Just for the heck of it...

 

Here's an example circuit using the LM3914 dot/bar IC to generate the sequence using a 555 astable to generate the input quasi sawtooth:

View attachment 175611

When I suggested the sawtooth waveform as a trigger (post #27) I hadn't seen your post #19.

Why do you say that your configuration of the 555 generates a quasi sawtooth? The top waveform of your posted simulation looks exactly like a sawtooth to me.

The fact that you configured the 555 to generate a sawtooth wave sadly suggests that you understand exactly the functioning of the 555 . Me, I understand the logic of the 555 somewhat, but not to the point of being able to do what you did. So I tip my hat to you.

-Pete

 

Why do you say that your configuration of the 555 generates a quasi sawtooth? The top waveform of your posted simulation looks exactly like a sawtooth to me.

Look again. Notice that the width of each step gets longer as the waveform moves from left to right. That is an exponential waveform from the 555 timing resistor and timing capacitor.

ak

 

Why do you say that your configuration of the 555 generates a quasi sawtooth?

As AK noted, the waveform is actually part of the RC charging exponential (from about 1/3 to 2/3 of the total exponential amplitude, 0 to V+).
But the ramp can be made quite linear if the current to charge the cap comes from a constant-current source, (such as a two PNP transistor current-mirror), instead of a resistor.

Below is the LTspice simulation showing the charging ramp for the resistor (yellow trace) and current-mirror (blue trace) charging source.
The difference is quite apparent, with the blue trace looking like it was drawn with a straight-edge..
A linear ramp is useful for such things as generating a linear PWM signal with respect to the duty-cycle control voltage.

An interesting property of the current-mirror charging source is that it exhibits the same good frequency stability with changes in supply voltage as the resistor source.

 

Hey @crutschow would you run this on spice for me: I think it might work for your comparators...

Edit sorry this should be a 4 bit binary counter. I’ll fix it another time.

 

Here's an example circuit using the LM3914 dot/bar IC to generate the sequence using a 555 astable to generate the input quasi sawtooth:

View attachment 175611

Looking at your circuit today with a block diagram of the 555 timer at hand, how you use the 555 to generate a saw tooth waveform is fairly easy to follow. What puzzles me is that I have looked at quite a few different configurations of the 555 and never before saw it configured as you have done. The 555 periodically shorts capacitor C2 and removes the short.

In trying to understand the 555 some time ago, what I had difficulty following in detail was the operation of the two comparators in conjunction with the flip-flop of a 555 IC.

Thanks for your post,
Pete

 

The first comp. is triggered by a low, 1/3 Vcc, on pin 2, which sets the FF giving a high output on pin 3. Charging the timing cap. to a high, 2/3 Vcc, trips second comp. which resets the FF, making output low & enabling discharge, pin 7.

 

what I had difficulty following in detail was the operation of the two comparators in conjunction with the flip-flop of a 555 IC.

Here is the 555 operation, which is basically pretty simple, in a nutshell:

• The 555 flip-flop has a level-triggered set input (TRIG) which sets OUT to high when its voltage goes below about 1/3 the supply voltage.
• It also has a level triggered reset input (THRS) when resets OUT to low when its voltages goes above about 2/3 the supply voltage.
• When the THRS resets the FF, it also turns on the DIS terminal to discharge any capacitor on that node until either GND voltage is reached or the TRIG input is triggered. So anytime OUT is in the low state, the DIS terminal is connected to GND, and it is off (open-circuit) when the OUT is high.

And that's the basics.

To generate a significant OFF time for the 555 in the astable mode, you add a resistor in series the the DIS terminal to slowly discharge the cap.
In my case, I was interested in the fastest discharge time for the cap to generate a fast fall-time for the sawtooth, so I used no resistor.

Does that help?

 

@crutschow, your post #57,

Most of what you explained, except for how to configure it to make a significant OFF time, I previously read in the excellent text, Operational Amplifiers and Linear Integrated Circuits by Coughlin & Driscoll. I certainly don't expect an explanation from you, but for one thing I believe that I came to the conclusion that it made a difference if the RS Flip Flop was composed of either NAND or NOR gates.

If I weren't preoccupied with other things, I would like to construct a 555 from discrete components to better understand it. I haven't seen a detailed schematic diagram of the 555, or at least a circuit that is close to what a 555 actually is.

Thanks again,
Pete

.

 

Like this?

https://www.adafruit.com/product/15...5I_6LQivda4oB4GRYEByljQROBSKUS6BoCHAYQAvD_BwE

 

As above, there are several kits available that are an all-discrete 555 circuit 100% identical to the original. Search for "555 internal schematic" to find images like this:

ak