Hi,in the circuit numbers that come from counter are compared with 1 and the numbers are equal or greater than 1 led turns on.Also when the number reaches 9,it shouldn't move to 0(when press up button) and reaches 0 shouldn't move to 9.(when press down button)

On the breadboard upping works properly but downing does not.When the number is 0 and i press the down button,number downing 2 by 2.
I removed this "lock" gates from the circuit and then downed 1 by 1.The gates cause this problem.Could you help me?

 

With 74192 counters, the counter will count up or count down on the rising edge of the count input while the other count input is held HIGH. Have you ensured that the other count input is HIGH?

 

With 74192 counters, the counter will count up or count down on the rising edge of the count input while the other count input is held HIGH. Have you ensured that the other count input is HIGH?

Normally while counting down other input(count up) is low.
Just now i tried again, the circuit behaviour different,it comes down 1 by 1,so this is good,but now it continues from 0 to 9 when press down button.

 

Normally while counting down other input(count up) is low.
Just now i tried again, the circuit behaviour different,it comes down 1 by 1,so this is good,but now it continues from 0 to 9 when press down button.

You need to alter the logic so that the other count input is HIGH.

 

You need to alter the logic so that the other count input is HIGH.

Actually i did not understand what you mean,if continously logic 1 goes to 74192's up input,how can i up the number?

 

74192 counter IC has two clock inputs, UP and DOWN.
The counter counts up on the rising edge of UP while DOWN = HIGH.
The counter counts down on the rising edge of DOWN while UP = HIGH.

Make sure your logic satisfies these requirements. This demonstrates the importance of reading datasheets very carefully.

 

74192 counter IC has two clock inputs, UP and DOWN.
The counter counts up on the rising edge of UP while DOWN = HIGH.
The counter counts down on the rising edge of DOWN while UP = HIGH.

Make sure your logic satisfies these requirements. This demonstrates the importance of reading datasheets very carefully.

I checked,all the requirements are ok.In Proteus it works great but on the board i cant tell same thing.

 

Looking at your logic I do not see how the inactive clock input is held HIGH.

 

Normally while counting down other input(count up) is low.

And several times it has been mentioned that the IC won’t count down if the count up input is low!

 

Looking at your logic I do not see how the inactive clock input is held HIGH.

I've redesigned the circuit,still there is same problem.

 

And several times it has been mentioned that the IC won’t count down if the count up input is low!

I checked that logic 1 going to count up input.

 

How? The schematic you’ve given us, it’s hard to see how the input to the count up pin could be a 1?

 

How? The schematic you’ve given us, it’s hard to see how the input to the count up pin could be a 1?

Now you can check;

 

Are you designing your logic using a truth table or are you just guessing?

 

Are you designing your logic using a truth table or are you just guessing?

To prevent passing 0 to 9 and 9 to 0 i designed using truth table.

 

I see what you are trying to do... but I also see that it won’t work.

Take one half of the problem. Once the count reaches 9, you want to disable counting up. How do you do that? By forcing the DN pin low as long as the count is 9. I see what you are trying to do, but explain to me why you used an OR gate? With an OR gate, the DN pin can still be triggered by a push button. More importantly, you cannot force any state on DN.

See what I mean?

You have a similar problem when the count reaches zero.

What can you do to fix the problem? Work on one half of the problem at a time. Just fix counting up!

 

I see what you are trying to do... but I also see that it won’t work.

Take one half of the problem. Once the count reaches 9, you want to disable counting up. How do you do that? By forcing the DN pin low as long as the count is 9. I see what you are trying to do, but explain to me why you used an OR gate? With an OR gate, the DN pin can still be triggered by a push button. More importantly, you cannot force any state on DN.

See what I mean?

You have a similar problem when the count reaches zero.

What can you do to fix the problem? Work on one half of the problem at a time. Just fix counting up!

There is no problem that disable from 9 to 0 when press the count up button.I want to disable passing 0 to 9 when i press the count down button.
How can i fix it without using or gate?

 

Now there is no problem,the circuit works properly,it fixed itself i think the problem cause from different value of voltage.Thanks for the helps.