Hi guys! Im also new here. I have been searching the net for a schematic diagram of an XOR gate (TTL and CMOS) but I could not find any. Help Please.
Ive seen the discussion about the logic gates but the XOR gate schematic was not included.

 

Please do not hijack threads. Always start a new topic for your questions.

This is the hijacked thread - http://forum.allaboutcircuits.com/showthread.php?t=17921

The link given supplied the schematic - http://www.play-hookey.com/digital/xor_function.html

 

An n-input CMOS XOR is simply n-times series-pMOS transistors on the pull-up and n-times parallel-nMOS transistors on the pull-down.

Dave

 

Sorry about 'hijacking' that thread.

I'm looking for a schematic with transistors (BJT, FET, MOSFET, etc) that is connected in such a way that it functions as an XOR GATE, something like this:

Thanks for helping me out.
I'm looking for it cos I have to design a Full Adder IC, its a course requirement.

*edit*
I only need a 2-input XOR gate.

 

An n-input CMOS XOR is simply n-times series-pMOS transistors on the pull-up and n-times parallel-nMOS transistors on the pull-down.

Dave

Does it look like an OR gate? How do I make them a pull-up and a pull-down? Where do I place the resistors?

 

Does it look like an OR gate? How do I make them a pull-up and a pull-down? Where do I place the resistors?

Sorry, I misread the question, you want exclusivity (not least my previous description was for NOR, and you above diagram correct puts the inverter on the back end to make it non-negating).

XOR in CMOS is little more tricky. For two-inputs (because it is easiest to explain this way) you need two pMOS pull-up paths to Vdd and two nMOS pull-down paths to ground:

The two pMOS pull-up paths to Vdd are:

1) Series-transistors gate driven by A and NOT(A).

2) Series-transistors gate driven by B and NOT(B).

The two nMOS pull-down paths to Ground are:

1) Series-transistors gate driven by A and B.

2) Series-transistors gate driven by NOT(A) and NOT(B).

If you draw the circuit and plot the truth table the output is XOR. There would be a slight change on the pull-downs of XNOR. Let me know if the layout isn't clear, or draw it up and upload it so I can check the layout.

Dave

 

See the attached for one way to do it.
The schematic on top is a single CMOS NAND gate, 4011.

By combining four NAND gates as in the lower diagram, you will have an XOR gate.

This approach may be somewhat more complex, but using NAND gates has the advantage of flexibility; you can combine NANDs to create any other logic gate. Once you've perfected building NANDs, you have a very useful basic logic gate.

See this WIKI entry: http://en.wikipedia.org/wiki/NAND_logic

 

Maybe i remenber exclusive or cmos try cd430a,b.
where datasheetlocator.com

 

Here's what I found

Is the Vss the ground for the circuit? and is the First 3 groups of CMOS the 'CMOS protection network (from left to right)?

 

Vss is the substrate voltage, which is also ground for this application.

See the note and paper on the protection network - http://www.semtech.com/products/ESD-Protection-CMOS-ESD-Protection.jsp.

 

I designed this XOR gate using the instructions I found here. I know there's still a lot of things that needs to be sorted out before I could call this one a FUNCTIONING XOR gate, so help please!

oh, and thnx guys for all the help!!!