Hi all! I hope I'm posting in the right section; if I'm not, I apologize. I have a problem with a project that I'm working on for my next exam.

I have designed a simple Ripple Carry Adder in ISE and, after having synthesized it for my FPGA, the report says that the "maximum combinational path delay" is about 15 ns.

Then, I designed a Robertson multiplier (a sequential circuit), which contains an instance of my RCA. The report says that the "maximum combinational path delay" is about 7.5 ns and that the maximum frequency is about 130 MHz.

My question is: are these numbers right? Does the tool make some sort of "magic" optimization in order to "speed up" the adder inside the multiplier? Or is it just a wrong estimate?

I would have expected the minimum clock period for the multiplier to be at least equal to the adder's maximum delay, but it seems that it's not.

I also found out that if I select "Keep Hierarchy" to "Yes", in the Synthesis Options, the frequency in the report becomes more or less consistent with the RCA's delay.

 

I don't think we have nearly enough information to really answer you. The synthesis tool looks for design patterns and some of those it knows how to optimize and some of those it doesn't (or not as well). It's quite conceivable that by allowing it to ignore the hierarchy your design ended up using a recognized pattern in which part of it came from the adder and part of it came from the multiplier and it was able to optimize the combination.

If the delay number are post place and route, then you add in a whole new can of worms because the routing may be very different each time you run it, particularly if there is other circuitry that is added/removed/changed. Even changing a pin assignment can have a noticeable impact on the routing delay of completely unrelated circuits.