Hi. Does anybody know why my professor sets the GIE bit as 0 in the beginning of the intterupt function? Shouldn't it be set as 1 for the interrupt to work?

 

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Hi. Does anybody know why my professor sets the GIE bit as 0 in the beginning of the intterupt function? Shouldn't it be set as 1 for the interrupt to work?

https://ww1.microchip.com/downloads/en/DeviceDoc/31008a.pdf

The Global Interrupt Enable bit, GIE (INTCON<7>), enables (if set) all un-masked interrupts or
disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register. The GIE bit is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE
bit, which allows any pending interrupt to execute.
The INTCON register contains these interrupts: INT Pin Interrupt, the RB Port Change Interrupt,
and the TMR0 Overflow Interrupt. The INTCON register also contains the Peripheral Interrupt
Enable bit, PEIE. The PEIE bit will enable/disable the peripheral interrupts from vectoring when
the PEIE bit is set/cleared.
When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the
return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt
service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits.
Generally the interrupt flag bit(s) must be cleared in software before re-enabling the global interrupt to avoid recursive interrupts.
Once in the interrupt service routine the source(s) of the interrupt can be determined by polling
the interrupt flag bits. Individual interrupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.

Your professor sets the GIE bit to 1 as the ISR completes the instructions and then returns ready for the next interrupt.

 

Thanks!

 

This is inside the interrupt handler. The interrupt has already been triggered.

GIE = 0 and GIE =1 in the interrupt handler are unnecessary. GIE is cleared on interrupt and then set on return from interrupt automatically by the processor.

 

https://ww1.microchip.com/downloads/en/DeviceDoc/31008a.pdf


Your professor sets the GIE bit to 1 as the ISR completes the instructions and then returns ready for the next interrupt.

But this means that setting the GIE as 0 is not needed. As the pic does that by itself right?

 

For a normal hardware interrupt and interrupt handler its done automatically but I've created interrupt functions that are also called in the main context and used GIE clear and set to shield critical sections (non-atomic or time sensitive instruction sequences) from other interrupts. No idea why the prof is using belts and suspenders with GIE in that code.

disable interrupts
critical action
enable interrupts

 

I'd love to see the resulting .asm. GIE=1 in the handler will likely result in a race condition if another interrupt is triggered at any time after the GIE=0 and before the context switch back is complete.

 

I'd love to see the resulting .asm. GIE=1 in the handler will likely result in a race condition if another interrupt is triggered at any time after the GIE=0 and before the context switch back is complete.

Joey is spot on here. That's the reason for the atomic RETFIE instruction that the compiler will use at the end of the declared interrupt handler.

The learned professor has whiffed this one.

 

Joey is spot on here. That's the reason for the atomic RETFIE instruction that the compiler will use at the end of the declared interrupt handler.

The learned professor has whiffed this one.

It has been my experience that most of them are NOT as smart as they think they are. Most of them are legends in their own minds.