Hi, i have been trying to o a all transistor binary counter using d latches but my pcb doesn't work. When i test it on simulation program everything is all right. Can you help me see where i have made a mistake?

 

View attachment 307735

Hi, i have been trying to o a all transistor binary counter using d latches but my pcb doesn't work. When i test it on simulation program everything is all right. Can you help me see where i have made a mistake?

hint: review the output stage.

 

hint: review the output stage.

I dont get it. Should I delete the J1 output?

 

I dont get it. Should I delete the J1 output?

What will that change?

Go back and compare the logical elements in the logic diagram with your transistor version.

 

What will that change?

Go back and compare the logical elements in the logic diagram with your transistor version.

The only difference i can see is the lack of buffers but i don't think they change anything, but maybe this it the issue:

Is this resistor screwing me?

 

The only difference i can see is the lack of buffers but i don't think they change anything, but maybe this it the issue:

View attachment 307758 Is this resistor screwing me?

review the NOR truth table.
Does your transistor NOR adhere to the truth table?

 

review the NOR truth table.
Does your transistor NOR adhere to the truth table?

Looks good

 

on Breadboard works too

 

Try one of your NOR driving another NOR...

 

Try one of your NOR driving another NOR...

Works aswell

If someone knows the anwser please tell me directly

 

What simulator are you using?

The input to your transistor NOR gates is directly to the base of the transistor and the emitter is grounded. So the maximum
base voltage will be the Vbe of the transistor (and the current isn't limited). This will limit the output voltage of the stage driving
it to a "high" voltage of around 0.7 volts, much lower than Vcc.

 

What simulator are you using?

The input to your transistor NOR gates is directly to the base of the transistor and the emitter is grounded. So the maximum
base voltage will be the Vbe of the transistor (and the current isn't limited). This will limit the output voltage of the stage driving
it to a "high" voltage of around 0.7 volts, much lower than Vcc.

Thanks! i will try to break it down and understand what you said haha. For the simulation above i used https://logic.ly/demo/

 

So the solution will be to add like 2 inverters before Q17 the Vbe of it will be higher?

 

https://en.wikipedia.org/wiki/Resistor–transistor_logics

Notice the resistors on the imputs before the transistor bases.

 

So you are NOT simulating at the transistor level. The problem is that your basic transistor NOR gate is wrong so simulating
the logic using NOR gates doesn't show the problem but building with real transistors does.

Your NOR gate (built with transistors) should accept gnd or Vcc on each input and not load the inputs too much.
The output should switch between close to ground and Vcc.

PS: I'd prefer schematics with inputs toward the left, outputs toward the right, Vcc at the top and gnd at the bottom.
Your 1k collector resistors should go straight up and the NOR output should be to the right (not vertical).

 

https://en.wikipedia.org/wiki/Resistor–transistor_logics

Notice the resistors on the imputs before the transistor bases.

 

So you are NOT simulating at the transistor level. The problem is that your basic transistor NOR gate is wrong so simulating
the logic using NOR gates doesn't show the problem but building with real transistors does.

Your NOR gate (built with transistors) should accept gnd or Vcc on each input and not load the inputs too much.
The output should switch between close to ground and Vcc.

PS: I'd prefer schematics with inputs toward the left, outputs toward the right, Vcc at the top and gnd at the bottom.
Your 1k collector resistors should go straight up and the NOR output should be to the right (not vertical).
View attachment 307816

nice, i will try that on breadboard
What program do you use? does it simulate at the transistor level? (i use falstad also)

 

I use LTSPICE it simulates at the transistor level (and runs locally and is free).

In your #1 post diagram the transistors Q17 Q18 Q19 Q20 don't have resistors on their inputs so they
load down the outputs driving them. Also the LED4 doesn't have a resistor so it's going to load down
the output driving it. Perhaps the LED should have it's own driving transistor.

Also in #1 where are the D latch inputs?

 

I use LTSPICE it simulates at the transistor level (and runs locally and is free).

In your #1 post diagram the transistors Q17 Q18 Q19 Q20 don't have resistors on their inputs so they
load down the outputs driving them. Also the LED4 doesn't have a resistor so it's going to load down
the output driving it. Perhaps the LED should have it's own driving transistor.

Also in #1 where are the D latch inputs?

It actually suposed to be a d flip flop. I am trying to do a binary counter (i will add the resistors to Q17-20)

Now it works in falstad, but the led doesn't wanna turn off, but i think its the program fault because i can't do such a quick pulse

 

And Q12 in the upper left corner (NOT gate?).