Why does this prescaler says divide by 64 in the RF circuit diagram?

Thread Starter

dante_clericuzzio

Joined Mar 28, 2016
246
I would like to make this circuit based on the schematic diagram to get 3.5 Ghz frequency but i am not quite sure why it says on the diagram "Divide by 64" could anyone enlighten on this? Is it meant that 3.5 Ghz / 64 = 54.6875 Mhz?

prescaler-1.png
 

Sensacell

Joined Jun 19, 2012
3,432
1) it's not practical to build frequency counter chipsets that run at GHz frequencies, they would be super expensive and power hungry, etc.
It's much easier to have a separate prescaler / divider block that brings the frequency down to a range that is practical for standard digital chips to handle. This way you can have low-cost frequency counters that can go up to GHz range.

2) The simplest way to implement this divider is with cascaded flip-flops that divide by 2, 4, 8 ,16, 32 etc. as you add more cascaded stages.
These are typically implemented in a super-fast logic family like ECL, GaAs, etc.
 

Thread Starter

dante_clericuzzio

Joined Mar 28, 2016
246
1) it's not practical to build frequency counter chipsets that run at GHz frequencies, they would be super expensive and power hungry, etc.
It's much easier to have a separate prescaler / divider block that brings the frequency down to a range that is practical for standard digital chips to handle. This way you can have low-cost frequency counters that can go up to GHz range.

2) The simplest way to implement this divider is with cascaded flip-flops that divide by 2, 4, 8 ,16, 32 etc. as you add more cascaded stages.
These are typically implemented in a super-fast logic family like ECL, GaAs, etc.
Actually i am not trying to build a frequency counter...but RF amplifier...If you don't mind would you like to share any RF amplifier circuit that could amplify up to 2.6 Ghz / 4G LTE? I have build one which work but i think its still below average and i would like to have it work at least at average or above average.
 
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