Why does LTSpice do pesudo-trans. analysis when I change OP-AMP ?

Thread Starter

DarthVolta

Joined Jan 27, 2015
509
I have an integrator circuit that seemed to work ok with a u741, it doesn't run psuedo-trans. analysis, and I can run the sim for 20ms no problem with the PWL files I made.

So tried a TL072 just for kicks, and it has to run the psuedo-trans. analysis, that never seems to finish, so I hit esc, and right away it crashes with time step too small error. The TL072 is probably a model I DLed, from the recommended sources (if it's not included already).

I tried a LT1013, same problem as the TL072. So what's that mean ?
 

Papabravo

Joined Feb 24, 2006
14,399
Just for the sake of clarity, can you tell me what you mean by a pseudo-trans analysis?
Post the ASC file, I'm curious as to the effect you are describing.
 

Thread Starter

DarthVolta

Joined Jan 27, 2015
509
1st it says 'stepping source', then is does 'Pseudo-transient analysis', I gather related to finding initial conditions, and often just a poor circuit.
This is a chopped up version of a circuit I shall not name, the PWL files aren't perfectly synced, but the u741sim would run normal enough, so what changes so much with the other 2 op-amps, that it breaks the sim (of a circuit I cut stuff out of it to see what happens), but nevermind that, I'm just wondering in general?
 

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Papabravo

Joined Feb 24, 2006
14,399
This design is a hot mess and won't simulate at all due to a missing model for PN5434. You still have not clarified the meaning of a pseudo-transient analysis. I'm asking you: "what do you think it means?"

EDIT: Never mind I found it and it is looking for an initial operating point. My guess as to your problem is that the 741 is old and slow and is not causing a problem, whereas the faster more modern opamps are quite sensitive to the initial conditions and won't do well given the number of components and nodes that you have. If you want a suggestion you should add circuitry that holds all voltage levels constant at prescribed values until after a RESET signal is released.
 
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