Why do my counter ICs (e.g. 74LS163, 74LS169) not start at zero?

Thread Starter

zacgarby

Joined Sep 8, 2019
1
I'm trying to build a circuit which can count from 0 to 15 using a 74LS163AN IC. I've added a picture below to show you the circuit I made, and its initial state when I attach 5V from a USB cable.

All of the LEDs immediately turn on. It's almost always the case that all four outputs are high at the start, but sometimes it's all but the most significant bit, and it can be different to that as well rarely. With the 74LS169 (and a similar circuit), the initial state is even less predictable.

Surely, this can't be the expected behaviour of these chips? I have tried multiple 74LS163s but they all have the same outcome. Am I wiring it up wrong?

Or if this is expected, what's the best way to fix this problem (i.e. set it to zero as soon as possible)?

IMG_2697.jpg
 

crutschow

Joined Mar 14, 2008
23,347
Surely, this can't be the expected behaviour of these chips?
Yes it is.
The IC will come up with a random state of the internal FF's since there is nothing to insure that they come up in a specific state upon power up.
To set them all to zero you need to use the SR (synchronous reset) pin 1, along with a clock-pulse during power-up. (see data sheet).
 

dl324

Joined Mar 30, 2015
8,913
Welcome to AAC!
Surely, this can't be the expected behaviour of these chips? I have tried multiple 74LS163s but they all have the same outcome. Am I wiring it up wrong?
It will power on in the reset state if you include a power on reset circuit.
 

djsfantasi

Joined Apr 11, 2010
5,600
Tell me -- what is the power on state of a counter like the LS163? Doesn't it depend on the clock?
IMHO...

Dl324 isn’t referring to the power on state. He’s referring to the stable state after a power on reset circuit resets the chip.
 

WBahn

Joined Mar 31, 2012
24,693
IMHO...

Dl324 isn’t referring to the power on state. He’s referring to the stable state after a power on reset circuit resets the chip.
I think the point that PB is making is that normally a power on reset circuit works by asserting a chip's asynchronous reset pin, often via a simply RC delay circuit on the asynchronous reset pin. But this chip doesn't have such a pin. Instead, a power on reset circuit would need to either exercise both the synchronous reset input and the clock input (which would generally defeat the purpose of using a fully-synchronous chip since you've now created a gated-clock) or it would have to be state-aware so that it would assert the synchronous reset input long enough to ensure that it had seen at least one valid clock after the set-up time requirements had been met. If you know the behavior (i.e., existence and minimum speed) of the clock after power on then you could probably still get away with using an RC delay on the synchronous reset, but it leaves open the door for problems if, for whatever reason, the clock start is delayed or the clock rate is every reduced significantly.
 

Papabravo

Joined Feb 24, 2006
12,405
I think the point that PB is making is that normally a power on reset circuit works by asserting a chip's asynchronous reset pin, often via a simply RC delay circuit on the asynchronous reset pin. But this chip doesn't have such a pin. Instead, a power on reset circuit would need to either exercise both the synchronous reset input and the clock input (which would generally defeat the purpose of using a fully-synchronous chip since you've now created a gated-clock) or it would have to be state-aware so that it would assert the synchronous reset input long enough to ensure that it had seen at least one valid clock after the set-up time requirements had been met. If you know the behavior (i.e., existence and minimum speed) of the clock after power on then you could probably still get away with using an RC delay on the synchronous reset, but it leaves open the door for problems if, for whatever reason, the clock start is delayed or the clock rate is every reduced significantly.
This was the crux of the question since it seemingly requires a one-shot reset shortly after power is applied. This is not the only solution. Other solutions involve a periodic reset or parallel load of a "starting" value whenever such an action is practical. This avoids the problem of designing a circuit which is activated only once and never thereafter.
 

crutschow

Joined Mar 14, 2008
23,347
If he really needs a power-on reset, it would greatly simplify the circuit if he used the 161, which has asynchronous reset, instead of the 163, which has a synchronous reset requiring a clock as well as a reset input.
 

danadak

Joined Mar 10, 2018
3,577
This is one of the problems with traditional discrete logic circuits. Even processors
of yore had this problem, power up unknown state and/or glitches.

Newer processors, FPGAs, ASIC can now be easily designed to avoid this design
problem.


Regards, Dana.
 

AnalogKid

Joined Aug 1, 2013
8,103
Note that the circuit in post #1 has no power supply decoupling, AND the four preset inputs are floating. If it truly is an LS part, the inputs float to the high state. Even with the PE* input tied high, the consistent 1111 power-on state might be due to an internal meta-stable or race condition load signal.

If the component choices are not cast in stone, to me the easiest answer is to change to the LS161 and add a simple R-C power-on reset. Or something with two 555's and a PIC.

ak
 

dl324

Joined Mar 30, 2015
8,913
I think the point that PB is making is that normally a power on reset circuit works by asserting a chip's asynchronous reset pin, often via a simply RC delay circuit on the asynchronous reset pin.
A power on reset circuit is whatever it needs to be. Sometimes it's as simple as the circuit you mentioned, sometimes it isn't. In the case of LS163, master reset needs to be held low and a clock pulse is required because reset is synchronous.
 
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