The 74LS163 is a completely synchronous counter, that means all updates of the states occur when the clock CLK is activated. The circuit is a 4 bit counter, that means it has 2^4 = 16 states. Every state sj, is given by the fourtiple Q = (qd, qc, qb, qa), where qa is least significant, as is binary code of the state index j. In the figure of the counter the available inputs and outputs are shown.

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The counter is affected by the input vector ( CLEAR', LOAD', P, T, D, C, B, A) according to the table:

Except that the state variables are available there is yet another output RCO (Ripple Carry Output). It is given by the following:

RCO = qd ^ qc ^ qb ^ qa ^ T.
("^" = "AND")

So RCO becomes 1 when the counter should go from 15 to 0. This can be used to construct a counter with other lengths than 16.

Task 1
Let the counter's input be (1, RCO', 1, 1, d, c, b, a) where the date signals a, b, c, d comes from a binary coded number according to number=(d, c, b, a).

Since the counter no longer restarts from zero it is now a modulo-X counter. Express X using the specified number number.

X = f(number) =____________________

Task 2
Realize a modulo-10 and a modulo-2 counter, according to the previous task.

Assume that the counters are clocked with the 2Hz clock. How should they be connected to get two output signals with the frequencies 1 and 0.1 Hz respectively?

Draw a schematic of the interconnection of the counters. Observe that the system should be synchronous, that means both counters should use the same clock.

How do you solve these tasks? If we start with the first one, what happens when RCO' goes into LOAD? What does that do? What does LOAD mean? What does parallel LOAD mean? How can we from this express X using number?

For the second task, to make a 2Hz counter to create output signals that are 1 and 0.1 Hz respectively. There should be some delay that makes the first signal count only count once when the clock counts twice, and the second signal should only count once every 20th time the clock counts. So I guess there must be some circuit that creates this delay. But what kind of circuit does that?

Please help the best you can

 

You approach these tasks one step at a time. You asked:

what does it mean that RCO goes into LOAD?

It is actually RCO'. That little tick mark on the end means "the complement of RCO". In real terms it means you run a wire form RCO' to Load'. If RCO is not available, then you need an inverter to create it from RCO. That's what it means. Does that help you?

 

You approach these tasks one step at a time. You asked:

what does it mean that RCO goes into LOAD?

It is actually RCO'. That little tick mark on the end means "the complement of RCO". In real terms it means you run a wire form RCO' to Load'. If RCO is not available, then you need an inverter to create it from RCO. That's what it means. Does that help you?

I know the ' sign means the signal is inverted. So no that doesn't help.

 

So do you now know that "RCO goes into load" means connect the RCO output to the LOAD input?

 

You come here asking for help and the first thing you do is make your transcription mistake my fault. Copping an attitude will put you on the fast track to stony silence.

 

You come here asking for help and the first thing you do is make your transcription mistake my fault. Copping an attitude will put you on the fast track to stony silence.

You asked if it was helpful that you pointed out that I missed a '-sign, and I simply answered honestly. I'm sorry if that offended you.

So do you now know that "RCO goes into load" means connect the RCO output to the LOAD input?

Yes. What I wonder is what happens when RCO' goes into LOAD'. As well as the other questions that I wrote, please see above.

 

Except that the state variables are available there is yet another output RCO (Ripple Carry Output). It is given by the following:

RCO = qd ^ qc ^ qb ^ qa ^ T.
("^" = "OR")

So RCO becomes 1 when the counter should go from 15 to 0. This can be used to construct a counter with other lengths than 16.

Are you sure that "^" = "OR"? Does that make sense? You are claiming that RCO=1 if ANY of those five signals is 1. Really?

What does LOAD mean? What does parallel LOAD mean?

What does the table say they mean?

Have you tried reading the data sheet for this part?

You need to show YOUR efforts to work YOUR homework problems, not just ask others to do them for you.

 

The missing tick was an oh by the way and not the main point. The main point was that routing a signal like RCO' to an input like LOAD' allows for the possibility that the behavior just might be determined by RCO'. The value of the input to LOAD' determines weather the next clock pulse will cause the counter to COUNT or LOAD the value of the 4 inputs into the flip-flops that make up the counter. The answer was right in the state diagram you provided. Does that help you?

You might find the following table helpful
http://en.wikipedia.org/wiki/List_of_logic_symbols

 

Are you sure that "^" = "OR"? Does that make sense? You are claiming that RCO=1 if ANY of those five signals is 1. Really?

No, you are right. "^" of course means AND. I would actually have like to use the logic AND "∧" symbol, is there some way to quickly write this in the forum? (now I copy-pasted it from an external website)

What does the table say they mean?

I have seen LOAD used in many circuits but I haven't understood what it means, but I assume it means the same thing in all circuits and now I need to know what it means. I couldn't find it when searching. I don't understand what is says in the table for the parallel load. sj points to sdcba but isn't j = dcba? So what does this state transition mean? And why is it called parallel?

Have you tried reading the data sheet for this part?

I could do that but there wasn't any data sheet included in the task so I assumed it wasn't necessary to solve the tasks (in all other tasks where the datasheet was needed it has been included).

You need to show YOUR efforts to work YOUR homework problems, not just ask others to do them for you.

I think I have shown all that I can. I started by asking some questions that I need to know in order to understand the tasks properly. Before I understand more that it's hard to show more.

 

The string 'dcba' refers to the four inputs. When LOAD' is low the following happens on the clock edge

d --> Sd
c --> Sc
b --> Sb
a --> Sa
​

The inputs dcba represent a binary number in the range [0..15] with d being the most significant bit and a being the least significant bit. When LOAD is low then 'dcba' is loaded in parallel, ie all at the same time as the clock edge, into the state register Sj where j represents the set {d,c,b,a}.

 

The missing tick was an oh by the way and not the main point. The main point was that routing a signal like RCO' to an input like LOAD' allows for the possibility that the behavior just might be determined by RCO'. The value of the input to LOAD' determines weather the next clock pulse will cause the counter to COUNT or LOAD the value of the 4 inputs into the flip-flops that make up the counter. The answer was right in the state diagram you provided. Does that help you?

So if LOAD = 0 (LOAD' = 1) the counter counts, while if LOAD=1 (LOAD' = 0) the counter is given the value of the inputs?

So if LOAD is 0 to start with and the counter counts every clock pulse, let's say it counts 0,1,2,3 and then LOAD is switched to 1, the counter is no longer 3 but has the value of A,B,C,D? Correct? Then I wonder where do the input signals A,B,C,D come from? RCO is just one bit (1 or 0) so it can't be that...

 

A couple of things. In the symbol for the part you will notice the word LOAD has a bar over the top. This is difficult to represent in text. My attempt was to use the tick as a synonym for the overbar. When the input, LOAD_OVERBAR, is low the counter will load the inputs, not immediately, but on the next rising edge of the clock. When LOAD_OVERBAR is high the counter will count. Yes, P & T have to also be high as does CLEAR_OVERBAR.
In your example the counter value remains at 3 until the rising edge of the next clock. Just after the rising edge of the clock the outputs will be equal to the inputs.

There do exist counters that have an asynchronous load. In this case the counter value changes immediately and does not have to wait for a clock.

 

No, you are right. "^" of course means AND. I would actually have like to use the logic AND "∧" symbol, is there some way to quickly write this in the forum? (now I copy-pasted it from an external website)

Instead of using the more math-oriented conjunction and disjunction symbols, I would recommend using the more engineering-oriented AND and OR symbols, namely multiplication and addition symbols from "normal" math.

For AND, you can therefore say Y = AB = (A)(B) = A·B, while for OR you can say Y = A+B. The carat. '^', is generally used for ZOE (exclusive-OR).

I have seen LOAD used in many circuits but I haven't understood what it means, but I assume it means the same thing in all circuits and now I need to know what it means. I couldn't find it when searching. I don't understand what is says in the table for the parallel load. sj points to sdcba but isn't j = dcba? So what does this state transition mean? And why is it called parallel?

Sj is simply a notation for "the present state", while Sdcba means "the state where the outputs are 'dcba'." It is called "parallel" because all four of the inputs are transferred to all four of the outputs at the same time, as though each one had it's own pipe from input to output and all of these pipes are laid out in parallel. Some counters would have a serial load in which you have a single input and on four successive clocks you apply the four values to the input and they are transferred to the outputs one at a time, typically by shifting from one output to the next until all four are in place.

I could do that but there wasn't any data sheet included in the task so I assumed it wasn't necessary to solve the tasks (in all other tasks where the datasheet was needed it has been included).

Think about how silly this statement is. You don't know something and you can't determine the answer from what is given, but while you acknowledge that you could look at the data sheet you don't feel that you should have to and therefore won't even give that a shot. Yet, I suspect that your assignment didn't say that it was necessary to ask strangers on an internet forum, either, yet you don't have a problem doing that.

As it happens, all of the information you should need is included in the information you were provided, you just don't know how to interpret it, so it's not unreasonable for the task not to say that you should consult the data sheet, because you shouldn't need to. But if you WERE to look at the data sheet, you might see statements such as, "The LS160A/161A/162A/163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature," and, "When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock."

I think I have shown all that I can. I started by asking some questions that I need to know in order to understand the tasks properly. Before I understand more that it's hard to show more.

What you need to start by is making reasonable efforts to find the answers on your own, which should at least allow you to narrow your questions and better understand the answers you get in return. Remember, you are training to be an engineer, which means a problem solver, who will be expected to solve problems on your own. While it is not expected that you will be able to do that entirely at this point, you are expected to get in the habit of going as far down that road as you can.

 

I actually tried to find a datasheet but I didn't found one where the circuit looks like in figure 1 (see first attached picture).

So here's how I'm reasoning for task 1:

If d,c,b,a and T are all = 1 then RCO=1, and RCO'=0. If RCO'=0, that means LOAD'=0 which means the counter loads the values of the inputs d,c,b,a, so it loads the value 1111. It will still have this value as long as LOAD'=0. When LOAD' is changed to 1, the following happens. Since 1111 is the highest possible 4bit value before it switches to zero, that means the counter will restart at zero at the next clock pulse.

So then we have counter that counts up as long as LOAD'=1 and when LOAD switches to 0 the counter will stop counting as long as LOAD'=0.

But how is this a Modulo X counter, as the task suggests?

 

So here's how I'm reasoning:

If d,c,b,a and T are all = 1 then RCO=1

It doesn't say this at all. The signal d is an input signal. The signal qd is an output signal. They are not the same signal. The RCO description says nothing about signals d,c,b, or a. It talks about qd, qc, qb, and qa.

 

Ok, so:

When qd,qc,qb, qa and T are all then RCO = 1. This means we have the value 1111 which is the maximum 4bit number. When RCO = 1, RCO' = 0 which means LOAD' = 0 and the counter gets the value from the inputs d,c,b,a. If d,c,b,a are ALSO 1111 then qd,qc,qb and qa will stay at 1111 and nothing will happen? If d,c,b,a are other numbers than 1111 then the qd,qc,qb,qa get new values so RCO will change to 0 and RCO'1 to 1 => LOAD' = 1 and the counter counts from this value.

So it seems to me we have two possible states. Either the counter counts until 1111 when it gets new values or it stays at 1111?

So one could make a counter that counts from value d,c,b,a up to 1,1,1,1? But not a counter that counts from 0,0,0,0 to d,c,b,a?

 

I guess you could look at it that way, but why? You could also look at it as 16 possible states, each one being adequately described by saying that the counter counts from the state that was loaded up until 1111 and then repeats. If the state that is loaded happens to be 1111, then this is still happening, you just don't see a difference in the outputs while it takes place.

Do yourself a favor and go read the datasheet and get familiar with this part.

 

I guess you could look at it that way, but why? You could also look at it as 16 possible states, each one being adequately described by saying that the counter counts from the state that was loaded up until 1111 and then repeats. If the state that is loaded happens to be 1111, then this is still happening, you just don't see a difference in the outputs while it takes place.

So are you saying that 1111 doesn't mean the number 15? I mean if the counters counts from let's say 0101 (5) to 1111 (15) then I would say it counts from 5 to 15. Are you saying that one should see it as 0 to 10 even that's not the binary coding? I.e. a modulo 10 counter?

Do yourself a favor and go read the datasheet and get familiar with this part.

I actually tried to find a datasheet but I didn't found one where the circuit looks like in figure 1 (see first attached picture).

 

So are you saying that 1111 doesn't mean the number 15? I mean if the counters counts from let's say 0101 (5) to 1111 (15) then I would say it counts from 5 to 15. Are you saying that one should see it as 0 to 10 even that's not the binary coding? I.e. a modulo 10 counter?

That wasn't what I was saying, but you could almost look at it that way, except it would be a modulo-11 counter (it has 11 states, 5,6,7,8,9,10,11,12,13,14,15). There's nothing that says that a mod-N counter has to use the N principle residues.

I'm saying that, using the description you were most recently talking about, you have 16 possible configurations. Counting from 5 to 15 and repeating is one of them. Counting from 0 to 15 and repeating is another. Counting from 15 to 15 and repeating is yet another.

I actually tried to find a datasheet but I didn't found one where the circuit looks like in figure 1 (see first attached picture).

And that is probably good, since you are having trouble understanding the presentation in Figure 1. Perhaps if you look at a data sheet that presents it another way, it will make sense to you. Since all of the descriptions are for the same hardware that behaves the same way, you can then take that new-found understanding and apply it to the presentation in Figure 1 to better understand how that style of presenting the information should be interpreted.

 

That wasn't what I was saying, but you could almost look at it that way, except it would be a modulo-11 counter (it has 11 states, 5,6,7,8,9,10,11,12,13,14,15). There's nothing that says that a mod-N counter has to use the N principle residues.

I'm saying that, using the description you were most recently talking about, you have 16 possible configurations. Counting from 5 to 15 and repeating is one of them. Counting from 0 to 15 and repeating is another. Counting from 15 to 15 and repeating is yet another.

But counting from 0 to x, where x is a number other than 15 is not possible? The final number must always be 15, right?

Now to task 2. I understand that there should be some delay that makes the first signal only count once when the clock counts twice, and the second signal should only count once every 20th time the clock counts. So I guess there must be some circuit that creates this delay. But what kind of circuit does that? Could it possibly be a bunch of D-elements in series? But that would require 20 of them in series for the 0.1 Hz-circuit though, which i doubt is the asked for solution since we are supposed to build this circuit with a more limited number of components. Any suggestions?