I am trying to understand how the 74ls163 works. I am building a z80 computer and added on a serial port using the attached schematic.

This print shows 307,692 hz comming out of the 74ls163 off pin Qd going to the RXc and TXc input to the 8251 USART. I built this circuit
and measured 4mhz coming from the clock circuit as shown but after the 74ls163 divides it down I am suppose to have 307,692 hz . I am measuring
907khz on pin Qd. I have checked the circuit wiring over and over but found no errors. I know this 74ls163 is a counter used to divide down the 4mz
but really have no idea of what is going on with it to do this division. It seems to have a 74ls00 as well that helps clear it out. Its just hard for me to look at it and tell how it works. I know it is 4 bit counter and that each flipflop divides by a different value. One Flip Flop = divide by 2 .. I think but can someone elaborate on what value it divides after that.

Could someone please help me understand this 74ls163 better in this circuit.
Thank you some much in advanced.

Mike

 

I am trying to understand how the 74ls163 works. I am building a z80 computer and added on a serial port using the attached schematic.

This print shows 307,692 hz comming out of the 74ls163 off pin Qd going to the RXc and TXc input to the 8251 USART. I built this circuit
and measured 4mhz coming from the clock circuit as shown but after the 74ls163 divides it down I am suppose to have 307,692 hz . I am measuring
907khz on pin Qd. I have checked the circuit wiring over and over but found no errors. I know this 74ls163 is a counter used to divide down the 4mz
but really have no idea of what is going on with it to do this division. It seems to have a 74ls00 as well that helps clear it out. Its just hard for me to look at it and tell how it works. I know it is 4 bit counter and that each flipflop divides by a different value. One Flip Flop = divide by 2 .. I think but can someone elaborate on what value it divides after that.

Could someone please help me understand this 74ls163 better in this circuit.
Thank you some much in advanced.

Mike

By what value does this circuit divide the 4mhz signal by?

 

It looks as though it should be wired as a divide by 13 counter.
The '163 has a synchronous reset, so it resets on the leading edge of the clock if the CLR pin is low.
So it counts 0 to 12, when 12 is detected (Qc and Qd are both high) then the output from the LS00 goes low, and it resets to zero on the next clock pulse, thus dividing by 13.

If yours is outputting 907kHz then it is working randomly, because divide by 4 would give 1MHz and divide by 5 would give 800kHz. So something must be loose.

 

Thats the answer I really needed. Thank you . As usual its the only chip I did not socket so I will just go over each pin again.

I think that you must be correct. Thanks so so .... MUCH.
Mike Wendt

 

Hi MW,
Check your 4MHz and other clock rise/fall times, I suspect they are low.

Update:
What chip type is the Master clock?

I assume you have adequate decoupling on the IC's power rails?

E

 

Just looking at @ericgibbs 's simulation here. Qb has three pulses for every one on Qd, which would be 923kHz. Are you sure you are measuring the 307kHz in the right place?

 

The counter has 13 states starting with 0000. When the counter reaches 1100, Qd and Qc will both be HIGH and the counter will reset to 0000 on the next clock pulse. The logic of the LS00 NAND gate is "a HIGH and a HIGH is a LOW". From there it is easy to compute:

\( \cfrac{4\times 10^6}{13}\;=\;307,692.3077 \)

Close enough for government work!

Note also that if the counter should happen to get into states 1101, 1110, or 1111 it will correct itself by resetting to 0000 on the next clock transition.

 

The counter has 13 states starting with 0000. When the counter reaches 1100, Qd and Qc will both be HIGH and the counter will reset to 0000 on the next clock pulse. The logic of the LS00 NAND gate is "a HIGH and a HIGH is a LOW". From there it is easy to compute:

\( \cfrac{4\times 10^6}{13}\;=\;307,692.3077 \)

Close enough for government work!

For a UART it should divide down to 9600 baud, but it gives 9615, just 1.66us on a 8-bit word with start and stop bits, or 1/63 of a bit time.