But counting from 0 to x, where x is a number other than 15 is not possible? The final number must always be 15, right?

What makes you think the final number must always be 15? Let's say you want to stop at 12. How can you tell that you have counted to 12? (Hint: using the outputs qa through qd.) Once you've reached 12, how can you start counting over? (Hint: using LOAD_Overbar.)

 

What makes you think the final number must always be 15? Let's say you want to stop at 12. How can you tell that you have counted to 12? (Hint: using the outputs qa through qd.) Once you've reached 12, how can you start counting over? (Hint: using LOAD_Overbar.)

If qd,qc,qb,qa = 12 in decimal it means they are 1100 in binary. That means RCO is not on (see above for condition for RCO), so it won't affect LOAD which is necessary in order to reset the numbers. So it can't stop at 12.

Now to task 2. I understand that there should be some delay that makes the first signal only count once when the clock counts twice, and the second signal should only count once every 20th time the clock counts. So I guess there must be some circuit that creates this delay. But what kind of circuit does that? Could it possibly be a bunch of D-elements in series? But that would require 20 of them in series for the 0.1 Hz-circuit though, which i doubt is the asked for solution since we are supposed to build this circuit with a more limited number of components. Any suggestions?

 

You are making an assumption that RCO is the only input possible to LOAD. I am suggesting that another input, derived from the qa to qd outputs will get you what you're looking for.

I almost edited my last post to point out that my scenario did not use RCO.

 

You are making an assumption that RCO is the only input possible to LOAD. I am suggesting that another input, derived from the qa to qd outputs will get you what you're looking for.

I almost edited my last post to point out that my scenario did not use RCO.

I don't know.

Any suggestions for task 2?

 

But counting from 0 to x, where x is a number other than 15 is not possible? The final number must always be 15, right?

Sure it's possible, just not using the very simple connection topology you are talking about here. But what if you detected when the output was a particular value and used a bit of logic to produce the LOAD signal from that and then loaded a value of zero? But if all you are looking for are signals that are square waves at 1 Hz and o.1 Hz, what does it matter what binary value is associated with the states the counter goes through as long as it goes through the correct number of states?

Now to task 2. I understand that there should be some delay that makes the first signal only count once when the clock counts twice, and the second signal should only count once every 20th time the clock counts. So I guess there must be some circuit that creates this delay. But what kind of circuit does that? Could it possibly be a bunch of D-elements in series? But that would require 20 of them in series for the 0.1 Hz-circuit though, which i doubt is the asked for solution since we are supposed to build this circuit with a more limited number of components. Any suggestions?

What do the Q outputs look like if you simply run this counter in a free-running (i.e., "+1") mode with a 2 Hz clock?

 

You are making an assumption that RCO is the only input possible to LOAD. I am suggesting that another input, derived from the qa to qd outputs will get you what you're looking for.

I almost edited my last post to point out that my scenario did not use RCO.

While it is arguably open to interpretation, I'm pretty sure the intent is to perform these tasks using just the two counter ICs and nothing else. At the very least, doing so is very straight forward.

 

Sure it's possible, just not using the very simple connection topology you are talking about here. But what if you detected when the output was a particular value and used a bit of logic to produce the LOAD signal from that and then loaded a value of zero? But if all you are looking for are signals that are square waves at 1 Hz and o.1 Hz, what does it matter what binary value is associated with the states the counter goes through as long as it goes through the correct number of states?

It would be interesting to know how to do that even though it's not part of the tasks. I guess it would be enough if the outputs qd,qc,qb,qa are connected with some logic gate(s) that gives the output 0 for the specified number (xxxx), and then connect this to LOAD, so that when this number is reached, LOAD goes to 0 and starts at whatever the inputs are.

What do the Q outputs look like if you simply run this counter in a free-running (i.e., "+1") mode with a 2 Hz clock?

Well, won't it also be running at 2 Hz? Or maybe it's actually already 1 Hz, if there are two D-element for each bit of q? Or am I completely wrong here?
What about 0.1 Hz? That would require 20 D-elements...

 

You can count from 0 to x by using a decoder to decode the value x and either activating the CLEAR_OVERBAR input, or the LOAD_OVERBAR input with dcba = 0000. As you might suspect you can also count from x to y, by loading x whenever you decode y.

 

While it is arguably open to interpretation, I'm pretty sure the intent is to perform these tasks using just the two counter ICs and nothing else. At the very least, doing so is very straight forward.

I need to caveat that the task allows the use of inverters to go from RCO to LOAD' and I neglected to take that into account.

 

It would be interesting to know how to do that even though it's not part of the tasks. I guess it would be enough if the outputs qd,qc,qb,qa are connected with some logic gate(s) that gives the output 0 for the specified number (xxxx), and then connect this to LOAD, so that when this number is reached, LOAD goes to 0 and starts at whatever the inputs are.

This is basically the idea. A common mistake that people make is they decode the desired number okay but then inadvertently decode other values as well.

Well, won't it also be running at 2 Hz? Or maybe it's actually already 1 Hz, if there are two D-element for each bit of q? Or am I completely wrong here?
What about 0.1 Hz? That would require 20 D-elements...

Don't guess. Draw a timing diagram that shows the clock and the qd, qc, qb, and qa outputs. That's only five signals. If the clock looks like a square wave at 2Hz, what do tehother signals look like?

 

I actually tried to find a datasheet but I didn't found one where the circuit looks like in figure 1

try this link ...

http://www.google.com/#q=74ls163

You might not ever see the "same" drawing as you have in your first figure.