Hi, I'm working with RS flip flop on multisim (also built it form logic gates) and I have a question about it: Why 11 state on input is forbidden when in my program it works (only if on input I have 10 11 01 00 signals - like Grey code) and it generates Q = ~Q = 1
Also my simulation don't work when on input I have 00 signal first. What would happend in real circuit?

 

In the abstract case you are commanding the device to do something it cannot do, be in both the "1" or "set" state, and be in the "0" or "reset" state. at the same time. What it does is normally enforced by a feedback path. With both feedback paths in operation the device will have difficulty settling into a stable state. What an actual device might do after the invalid input condition is removed depends on the process technology e.g. TTL, CMOS, ECL, and temperature and other external influences. It is therefore indeterminate. This is a bad thing for a system to do.

Checkout the following article:

https://www.electronics-tutorials.ws/sequential/seq_1.html

 

Asserting both inputs is a metastable state:

 

Usually with homework help people get ask "well, what do you think ..." In this case, the details are sufficiently obscure that I'll answer directly.

I'm assuming you are talking about a flip flop made with cross-coupled gates.

11 as input is not really forbidden and as you have determined it produces a predictable and consistent output state. What it does do is break the notion that the outputs are complements of each other. One thing to think about here is what might happen if you de-asserted both inputs at exactly the same time.

With regard to startup with both inputs de-asserted: In a simulation, parts are absolutely identical unless you somehow force them to be otherwise - input threshold voltages for logic levels, output voltages versus logic state and loading, propagation delay times, etc. all absolutely identical. When you turn on the power in a simulation, unless you specify otherwise or have some components in the circuit that make it otherwise, it rises instantaneously from zero to nominal. This can produce an interesting situation where neither gate "knows" what it is "supposed to be doing" - you can get into a permanent stable state with bad logic levels and never get out of it. In real circuits, there will always be a little bit of difference in the components and even if they were identical, there would be some electrical "noise" simply due to the fact that noise is produced by resistors. These things will normally force the circuit one way or the other, though not necessarily instantaneously. If you were to add a small resistance between the output of one gate and the input of the other, and prehaps add a tiny capacitance or high value resistor to ground at the input to which the resistor is connected you would probably see the simulation settle to proper logic levels at power up.

 

It is actually important to realize that this so-called "forbidden" input condition really isn't forbidden and will produce known output conditions in most cases, simply because that condition can sometimes arise in real circuitry and you need to know how it will behave.

 

"Forbidden" may be a misleading term.
The 11 state is, in the abstract, undefined for an RS flip-flop, thus is not normally "allowed" in a logic sense.

In reality, a particular flip-can may go to a particular state for that input or it may oscillate, depending upon the design of the flip-flop.
For example, the CD4013 D-FF truth-table below has a defined output for a 11 RS input (both outputs logic 1):

 

Hi, I'm working with RS flip flop on multisim (also built it form logic gates) and I have a question about it: Why 11 state on input is forbidden when in my program it works (only if on input I have 10 11 01 00 signals - like Grey code) and it generates Q = ~Q = 1
Also my simulation don't work when on input I have 00 signal first. What would happend in real circuit?

The reason that it doesn't work when you start with 00 signal is that you are asking it to hold the prior output but it doesn't know what the prior output is. This is a problem with simulators since a real circuit WILL have a prior output, even if you can't predict what it is. The problem with a 11 input isn't that the circuit's behavior is undefined while those inputs are asserted (it may or may not be, but usually is), it's that if you take it to 00 in the next step the behavior is undefined due to a critical race condition. This race is resolved in the real world and the result is one of two possible states (though it might result in metastability for a while -- look up that concept), but you can't predict what it is.

Anything that results in circuits doing things you can't reliably predict are bad circuits (unless that's the point of the circuit), so things that lead to that behavior are often described as "forbidden" conditions.

 

Hi,

Sometimes it's not even about predictability it's about the way it is intended to be used.
In this case, if you have a '1' on the Q output and also a '1' on the Q_not output then that may be considered to not be a real Flip Flop anymore because a real Flip Flop always has one output being the invert of the other.
So by stating that some input combination is not allowed they are really saying that you would not really want to do that if you are using this as a real Flip Flop. Of course for some applications this may not matter, but that's not the point of view of the Flip Flop proper.

 

Hi,

Sometimes it's not even about predictability it's about the way it is intended to be used.
In this case, if you have a '1' on the Q output and also a '1' on the Q_not output then that may be considered to not be a real Flip Flop anymore because a real Flip Flop always has one output being the invert of the other.
So by stating that some input combination is not allowed they are really saying that you would not really want to do that if you are using this as a real Flip Flop. Of course for some applications this may not matter, but that's not the point of view of the Flip Flop proper.

Most real circuits deal with this by buffering the outputs of a building block like this, so you would have two inverters in series off of just the Q output (or just Q' output, but not both) and the outputs of the inverters would be the FF outputs. That effectively guarantees that the outputs are always complements of each other. It also prevents loading of the outputs from affecting the state of the FF, which is another issue with most basic FF building block circuits.