Hi,

I created the following circuit here.




The DIM Control Pin sources a 10uA current. I am getting 0.5V of noise on that pin (looking at the oscilloscope). It probably has to do with the GNDA being connected to the MOSFETs. And probably to do with my PCB layout.

Currently, I don't have CF3, CF4, CF5, CF6 installed on the PCB. When I added CF5 and CF6 using leaded MLCCs, it did help reduce the peak to peak noise a little.

Below shows each individual DIM control pin. One has a 1uF on it (CF5), the other doesn't (missing CF6).


If anyone has good experience with MOSFETs, noise, and PCB layout, it'd be great to have someone take a look and offer suggestions on how to reduce the noise further and any changes to the PCB layout. It's my first circuit design, so, be gentle.....

Thanks for your time.

 

Hello there

Currently, I don't have CF3, CF4, CF5, CF6 installed on the PCB

My friend what are you thinking? This is directed to MIT open source schematics.At glance of this circuit five errors.It is not your mosfets...
op-amp circuit uses a feedback capacitor to limit the bandwidth. Limiting op-amp bandwidth will reduce noise, so a feedback capacitor is a common way to reduce noise. To understand how the feedback capacitor works, consider that a capacitor acts as a short to “high frequency” AC signals. Thus, at high frequencies the noise gain will reduce gain to unity.