Whats the equivalent of this while() loop [in verilog]

Thread Starter

linux2k

Joined Dec 13, 2008
3
I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as:

Rich (BB code):
while (num < test_number) 
     begin 
     . 
     . 
     . 
     num = num+1; 
     end
This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as unbounded parameter. Either way, its a bad coding habit. But I'm so used to doing this in C and testbenches. What would be the equivalent synthesizable of code of the above code segment?

Thank you
 

russ_hensel

Joined Jan 11, 2009
825
I have been programming for a long time and never heard of "synthesizable code". Seems to have some specialiced application. However googling it seems to give a lot of references, why not give it a try.
 
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