Whats the equivalent of this while() loop [in verilog]

Discussion in 'Embedded Systems and Microcontrollers' started by linux2k, Mar 1, 2010.

  1. linux2k

    Thread Starter New Member

    Dec 13, 2008
    I've gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I've taken this habit over to coding for circuits which should be synthesizable. XST and others refuse to synthesize code (without additional modification to synthesis parameters) such as:

    Code ( (Unknown Language)):
    2. while (num < test_number)
    3.      begin
    4.      .
    5.      .
    6.      .
    7.      num = num+1;
    8.      end
    This is bad coding style because to the synthesizer test_num is an int with value 2^32! or it sees it as unbounded parameter. Either way, its a bad coding habit. But I'm so used to doing this in C and testbenches. What would be the equivalent synthesizable of code of the above code segment?

    Thank you
  2. russ_hensel

    Distinguished Member

    Jan 11, 2009
    I have been programming for a long time and never heard of "synthesizable code". Seems to have some specialiced application. However googling it seems to give a lot of references, why not give it a try.