Does this notation (highlighted below) in a schematic mean that 3 of these caps will need to be placed in parallel?

Seen in an Analog Devices datasheet where they are detailing a typical application schematic. Sorry if this question has been asked before. I can't seem to find an answer anywhere. Thanks in advance.

Seen in an Analog Devices datasheet where they are detailing a typical application schematic. Sorry if this question has been asked before. I can't seem to find an answer anywhere. Thanks in advance.
