weird behaviour of a pow MOSFET on LTSpice, is it real?

Thread Starter

BulbChangeExpert

Joined Mar 26, 2016
54
i'm working on an H bridge with TO220 pow mosfets, it's actually a hobby project tought to be published online, after some effort to develop the "control" section with decent success i bumped on a weird and hardly replicable effect on the mosfet's gates, before building anything and wasting components and especially fuses i'd like to know if this effect is a LTSpice "bug" or it's a real word issue

when the upper Pmos closes very rapidly (1 us rise time) and the Nmos gate is held low the Pmos pulls the drain of the Nmos (obvious) but on it's turn the Nmos gate tries to pull high the control circuit with 1A actually succeeding and reaching 2.5V for a brief period, this closes the Nmos when the Pmos closes generating a tremendous current spike trought the two transistors

is it a real issue or i can ignore it and build the thing?
 

Thread Starter

BulbChangeExpert

Joined Mar 26, 2016
54
the incriminated section is this, but (again) it's hardly replicable, anything i change (from the circuit i actually want:rolleyes:) makes the effect go away or get minimized

the 2.5V appears on the lone wire there, even there's no circuit driving the NmosUntitled.jpg
 

Alec_t

Joined Sep 17, 2013
10,369
It would help if you label the relevant circuit nodes, so that we know which ones you're talking about, e.g the "lone wire".
 

Thread Starter

BulbChangeExpert

Joined Mar 26, 2016
54
It would help if you label the relevant circuit nodes, so that we know which ones you're talking about, e.g the "lone wire".
you're right but i thought it was "simple"

here's the file, please excuse:::
-the mess
-the fact that it's not the actual circuit
-the (temporary) teorycity of the circuit

how to track the "bug":::
run the circuit briefly, discard the obvious "crossover big current" of the two mosfets, look on the "gate" lable for little spikes of around +2V, zoom it, then test for the fact that current at that time is flowing from the Nmos to the 555 by testing from "gate" to "reference".... this happens when the Pmos turns on
 

Attachments

crutschow

Joined Mar 14, 2008
23,353
It appears to be feedthrough from the drain-source capacitance, as the source current spike equals the drain current spike.
It's not turning on the MOSFET. Even if you ground the gate to the source you will still see the current spike.
It's not an LTspice "bug", it likely will happen in a real circuit.
 

Alec_t

Joined Sep 17, 2013
10,369
I agree: drain-gate capacitance of the NMOS (M2) is the likely cause. Connect an external d-g cap (say >1nF) and you will see the gate spike increase.
 

Thread Starter

BulbChangeExpert

Joined Mar 26, 2016
54
this hipotesys is not new to me, (btw, you two are perfectly right) but when i said "hardly replicable" i meant that i tried to tie the Nmos gate to gnd trought a resistor and after the start of simulation it didn't happened (or it was negligible), so i tought it COULD be a software bug instead of a parasitic capacitance... but you are still right beacause the issue rises when this capacitance is dis\charged by turning the Nmos on and only after that the Pmos can pull a current trought the Nmos drain, in case the Nmos is tied to gnd (like in the jpg i posted) this capacitance stays dis\charged not causing this issue (a lot)
if you are not sure about my view just reply

thanks guys, i'll try to solve this problem (but i still need fast rise times), in case i fail i'll "appear" again

EDIT:
*you three
 

Thread Starter

BulbChangeExpert

Joined Mar 26, 2016
54
likely
but, i dunno, maybe it causes great noise (also RF noise?)
all this just if the DC motor doesn't increase the undesired effect like X10000 times....

however this project is starting to stink, i'll likely not finish it (because i really want to use low-tek components (to make it easily replicable))
 

mgdaubo

Joined Dec 8, 2016
4
Hi all, any update on this?

I think I am facing the same problem. Here is my simplify circuit to test only this:

capture.jpg

At the moment the switch turns ON, if the rise time is fast (0.01us), the Mosfet turns ON and leads to sharp spike 650mA in 0.1us. I think this is because the current flow through R2 and charge to Cgd of Mosfet, creates the voltage bias on Source-Gate and turns on the Mosfet.

Will this actual happen in real circuit, and how to avoid it (real circuit and simulation also)? Actually I am trying to make a soft start circuit with Mosfet and RC on Vgs, but it show a large spike initially when switch turns ON, makes the waveform looks very bad.

Any idea?

Thank you.
 

Attachments

crutschow

Joined Mar 14, 2008
23,353
It's the Cds you are seeing, which is likely a real thing.
The MOSFET is not turning on. Even if you short the drain to the gate you still see it.
A MOSFET with a lower Cds would lower the spike but I don't know how you would totally get rid of it.

The waveform may look bad but will such a short spike really affect your circuit?
What is the soft-start circuit driving?
 

mgdaubo

Joined Dec 8, 2016
4
Thank you for your fast response,

But I think mosfet is actually turning ON this case, you can see my waveform:
waveform.PNG

Vgs is about 1V which is enough to turn on the Mosfet (Vgs threshold = 0.6V).

My circuit is to limit the inrush current charging to the capacitor.

This leads me to confusion when I develop more complicated circuit which is basically an ORING and inrush current limiter. I see very large spike when the power sources switch ON/OFF, and I could not figure out whether that is because of this effect or actual response of my circuit.

Thank you.
 
Top