A word of warning.
Using the CD4000_v library with a circuit node labelled "vdd", all models should allow the external vdd voltage to over-ride their internal vdd parameter which, by default, is 5V. But for the CD4001 (a 2-input NOR), simulation behaviour depends on which of two NOR symbols is used in the schematic.
With the square box international symbol all is well and good .......

Here, the gate output voltage swings between 0V and 12V as it should, even though the vdd parameter in the model is the default 5V.
However, if the curved symbol is used, or merely present in the schematic, the output of the gate swings between 0V and 5V only ......

I haven't looked into the cause, but there seems to be a bug associated with that curved symbol. Any thoughts?
Update:
Problem sorted by editing the curved symbol to delete its Modelfile attribute.
Using the CD4000_v library with a circuit node labelled "vdd", all models should allow the external vdd voltage to over-ride their internal vdd parameter which, by default, is 5V. But for the CD4001 (a 2-input NOR), simulation behaviour depends on which of two NOR symbols is used in the schematic.
With the square box international symbol all is well and good .......

Here, the gate output voltage swings between 0V and 12V as it should, even though the vdd parameter in the model is the default 5V.
However, if the curved symbol is used, or merely present in the schematic, the output of the gate swings between 0V and 5V only ......

I haven't looked into the cause, but there seems to be a bug associated with that curved symbol. Any thoughts?
Update:
Problem sorted by editing the curved symbol to delete its Modelfile attribute.
Last edited: