We have a code for our fpga project we need you to modify the code to run run in basys 3 and the outputs will be given in the computer.

Thread Starter

vasanth2304

Joined Mar 5, 2024
4
Mod: added Code quotes.

C-like:
module image_overlay (

    input clk,

    input rst,

    input [7:0] image1_data, // assuming 8-bit grayscale image

    input [7:0] image2_data,

    input [7:0] overlay_mask, // 8-bit mask for overlaying

    output reg [7:0] combined_data,

    output reg vsync,

    output reg hsync

);


// Define image dimensions

parameter WIDTH = 320; // assuming 320 pixels width

parameter HEIGHT = 240; // assuming 240 pixels height


// Define counters for tracking image positions

reg [9:0] x_counter;

reg [9:0] y_counter;


always @(posedge clk or posedge rst) begin

    if (rst) begin

        x_counter <= 0;

        y_counter <= 0;

        combined_data <= 8'b00000000; // initialize combined_data

        vsync <= 0;

        hsync <= 0;

    end

    else begin

        // Increment counters

        if (x_counter == WIDTH - 1) begin

            x_counter <= 0;

            if (y_counter == HEIGHT - 1) begin

                y_counter <= 0;

            end

            else begin

                y_counter <= y_counter + 1;

            end

        end

        else begin

            x_counter <= x_counter + 1;

        end


        // Overlay logic

        if (overlay_mask >= 128) begin // if mask pixel is white (or close to it)

            combined_data <= image2_data; // overlay image

        end

        else begin

            combined_data <= image1_data; // otherwise, use base image

        end


        // Output synchronization signals

        if (y_counter == HEIGHT - 1 && x_counter == WIDTH - 1) begin

            vsync <= 1;

            hsync <= 1;

        end

        else begin

            vsync <= 0;

            if (x_counter == WIDTH - 1) begin

                hsync <= 1;

            end

            else begin

                hsync <= 0;

            end

        end

    end

end
endmodule
 
Last edited by a moderator:

Ya’akov

Joined Jan 27, 2019
9,267
Welcome to AAC.

While you’ve posted your question to the correct forum (since it is an assignment) your question is not acceptable.

As you should have learned from your last post, the rules of AAC only permit assistance with your work, not to do it for you. Please post your attempt to solve the problem, we can then help with guidance to make it work.

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