I want it to output 5 amps or so.

You do realize that with a 100V input the dissipation in the MOSFETS will be over 250W @ 5A.
Are the MOSFETs' heat sink(s) sufficient to handle that much power?

And note the safe operating area of the IRF621 below (black DC line).
At 50V drop (100V input), the most the transistor can safely pass is about 0.7A, so even with 4 perfectly matched transistors in parallel, the highest output current would be 2.8A.


Why such a wide input voltage range?

And why was the PCB made before breadboard testing of the circuit?

Sorry, but I don't think any quick-fix will get this circuit to do what you want.

 

Ok, so i was off on the frequency of the ripple. The input voltage is 62V right now. I sent you 4 screen shots, two with no load and the other 2 with 412 ohm load. The one with higher frequency ripple is with a load. Any ideas?

Hello again,

Can you get a shot of BOTH the output AND the output of the op amp on the same screen shot?

What happens in these circuits is the output changes and the control takes too long to recognize that change and so it continues to drive the output in the same (and now incorrect) direction. Compensation inside the feedback loop is what is needed, and that could be hard to obtain depending on what your output load will be because the output load becomes part of the circuit. If the output load changes, the response could change drastically so the compensation might have to change too.
This means for proper operation the load should be specified also, and hopefully it does not change as that makes it easier.

If you have never done anything like this before you would find it very informative to try to do a much simpler circuit with just an op amp and PNP transistor. You could start with an NPN transistor and see how nice that works, then switch to a PNP transistor (and appropriate other changes) and see the problem crop up. You then have to be able to compensate the circuit so it does not oscillate.
If you cant do that simpler circuit you will never do the more complicated one unless someone hands you the solution, if in fact one exists.
If i get a chance i will show you some examples.

 

Hello again,

Here are two circuits both the same really except one has compensation and the other doesnt.
Note the main idea here was to get the op amp to work better as a real integrator.
Speed of response has to be checked after this addition too.

The first circuit shows the response oscillation and then also a closeup of that oscillation.
The second circuit output damps out nice and smooth.
The load resistor in these circuits is R1.

 

It isn't easy to simplify.

Based on the waveforms (numbered for ease of reference):

1. the error amplifier (the op amp) "commands" the FETs to increase conduction to raise the output voltage
2. with light load, the FETs only have to be enhanced slightly to deliver sufficient current to meet the load requirement, but also adding charge to the output capacitors at the same time IF the voltage is allowed to rise
   
3. the error amplifier detects that the voltage has reached the setpoint and because it is fast and high gain it very rapidly commands reduction in the FET conduction, but ...
4. there are delays (delay in the time domain = phase lag in the frequency domain) in the circuit due to at least three separate RC circuits - R17 and C25, R13 and C19, and R13 and the capacitances of the FETs' gates so ...
5. the error amp has long since commanded reduction in the FET current, probably swinging its output to zero, but the delays prevent this from getting through to the FETs in time, so now you get gross overshoot of the setpoint
6. the error amp's output is now unquestionably sitting at the lowest voltage it can - the error amp is overdriven and acting as a comparator, which is a bad thing because that slows down its recovery to normal amplifying (but probably not really much a contributor here because other delays will be much larger)
7. the FETs respond and turn off completely (the actual response time can't be resolved at the time scales used)
8. slowly the overcharged output capacitors discharge through the load resistor and the voltage sense resistor chain
9. when the caps are sufficiently discharged the error amp's output will begin to rise to get the FETs to conduct again, but those same delays will come into play again and the voltage will probably drop to slightly below the set point
10. the error amp will now probably switch to having its output as high as it can go
11. the whole thing repeats

Each of those mentioned RC circuits introduces a time delay or "pole" in the response. There are two ways to deal with this (other than by eliminating unwanted poles where possible):

• make the frequency of one pole very low so that the gain of the loop drops to unity at a very low frequency. This can make the loop stable but very unresponsive - if there is a change in input voltage or output load it can take a long time for the circuit to repond
• compensate the poles by adding "zeros" which (on their own) cause phase "lead". Properly done this can result in good dynamic performance without oscillation or serious undershoot or overshoot problems

Again, the object is to make the overall gain of the closed loop pass through 0 dB "unity" (on its way down) with a total phase shift around the loop of no more than about 300 at that crossover frequency. This give 60 degrees of "phase margin" which results in pretty decent performance. If you get the loop frequency response set optimally, the slope of gain versus frequency for at least a decade or so below the crossover frequency would preferably be -20 dB per decade (-6 dB per octave). This slope also means that things that might mess with the crossover frequency are less likely to cancel that important 60 degrees of phase margin. The circuit won't oscillate with very low phase margin, but the dynamics will be poor with overshoots and undershoots.

One way to put a single zero into the response is to put a capacitor across R11. Try some smallish values of a few nanofarads to tens of nanofarads. Don't expect this to fix the problem, but you should see a change in behavior.

===
Paralleling the FETs has nothing whatever to do with the behavior at the frequencies seen. There are lots of issues with paralleling, but the low frequency oscillation isn't one of them.

===
If you are really lucky, Crutschow might simulate the circuit for you. If he does, be very grateful, because it will have taken quite a lot of work on his part.

===
Using 0.1% tolerance resistors with an ordinary zener diode as the voltage reference is a waste of money.

Thanks for the very detailed response. I am trying a few tests to see if I can get it working. This is very good information.

 

You do realize that with a 100V input the dissipation in the MOSFETS will be over 250W @ 5A.
Are the MOSFETs' heat sink(s) sufficient to handle that much power?

And note the safe operating area of the IRF621 below (black DC line).
At 50V drop (100V input), the most the transistor can safely pass is about 0.7A, so even with 4 perfectly matched transistors in parallel, the highest output current would be 2.8A.
View attachment 158790

Why such a wide input voltage range?

And why was the PCB made before breadboard testing of the circuit?

Sorry, but I don't think any quick-fix will get this circuit to do what you want.

I do have a heat sync solution. And I 2.8A way still be within the acceptable spec.I do not mind changing the MOSFETS, but I need to make sure the concept works first.

 

Hello again,

Can you get a shot of BOTH the output AND the output of the op amp on the same screen shot?

What happens in these circuits is the output changes and the control takes too long to recognize that change and so it continues to drive the output in the same (and now incorrect) direction. Compensation inside the feedback loop is what is needed, and that could be hard to obtain depending on what your output load will be because the output load becomes part of the circuit. If the output load changes, the response could change drastically so the compensation might have to change too.
This means for proper operation the load should be specified also, and hopefully it does not change as that makes it easier.

If you have never done anything like this before you would find it very informative to try to do a much simpler circuit with just an op amp and PNP transistor. You could start with an NPN transistor and see how nice that works, then switch to a PNP transistor (and appropriate other changes) and see the problem crop up. You then have to be able to compensate the circuit so it does not oscillate.
If you cant do that simpler circuit you will never do the more complicated one unless someone hands you the solution, if in fact one exists.
If i get a chance i will show you some examples.

I accidentally fried my board by adding cap across R16. LEt me get it back up and running and I can attach screen shots.

 

I mentioned putting a cap across R11. I shouldn't have without noting that this could cause overdrive of the op amp input. With no feedback around the amp, a series resistor of 20k between the op amp input and the junction of R11 and R16 will reasonably protect the amp input without making much difference in performance.

My inclination would be to eliminate C25 and C19 completely. I would add a capacitor from pin 6 to pin 2 of the op amp. I would try about 5 to 10 nanofarads, but I admit that this value is just a wild guess. A very large capacitance would probably make the circuit stable, but at the expense of very poor dynamic response. Doing this replaces two poles outside of the error amp with a single pole inside. Other poles still exist and one or more compensating zeros will likely be required. Be prepared for the circuit to oscillate, certainly at a different frequency and possibly with large amplitude.

It really would be very helpful to be able to simulate the circuit. LTspice (I think renamed now) is available free from Analog Devices and is very popular with folks at AAC.

AM-1148 from TI looks like it is worth a read for a good overview of gain and phase issues.
www.ti.com/lit/an/snva020b/snva020b.pdf

 

See

 

Here's an LTspice simulation of the basic circuit with compensation from R4, C1, and C2.
C2 is a Miller effect capacitor proving lag compensation, and C1-R4 provides lead-lag compensation.
Without the lead provided by R4 there was a significant peak in the AC response curve and the circuit was not stable.

R5, C3, and C4 were added to provide a soft-start and prevent overshoot at start-up.

The compensation and soft-start values were empirically determined during simulation.

As can be seen, the transient simulation is free of oscillations, and the AC Bode plot shows a smooth frequency response and rolloff with no significant peaks, all indications of stable loop operation (nominal output regulated voltage is 10V).

The 1A transient load, provided by I1, shows that the output transient recovery is quite good with no ringing (see expanded second trace), which is also indicative of a stable loop.

The actual circuit will likely require some tweaking of R4, C1, and C2 to get the proper response.

 

See

 

I optimized the circuit and greatly improved the ripple suppression ratio.Input ripple peak-peak 1V (100Hz), output 30.5uV.