Built this circuit on a PCB, but it is not regulating properly. It is set to regulate at 48V output (at 50V to 100V input). There is about a +/- 10 Volt swing at the output that looks like a ramp. How can this circuit be improved so that there is a 48V output of no more than a 500mV ripple and not a 10V ripple? Please help!

 

What frequency is the ripple you are seeing?

 

I do not have the board in front of me right now, but i wanna say 100kHz or so. I will not know until tomorrow. What are you thinking?

 

At 100 kHz, that isn't ripple. The circuit is unstable - an oscillator.

How much current is it supposed to handle?
What is the test current?
Have the FETs been precision matched for threshold voltage and transconductance?
Are the FETs very carefully mounted to make them all isothermal?

 

Are you using the printed values or handwritten component values, especially for R13, R17 and C25?

 

The P-channel Mosfet is common source so it has voltage gain that messes up the stability of the opamp that has the Mosfet in its negative feedback loop. A low dropout IC regulator also has this problem and fixes it with a fairly high value (100uF for some of them) output capacitor.

 

The P-channel Mosfet is common source so it has voltage gain that messes up the stability of the opamp that has the Mosfet in its negative feedback loop. A low dropout IC regulator also has this problem and fixes it with a fairly high value (100uF for some of them) output capacitor.

Hi,

Very well said AG

Just to add a little more info...

This also happens with PNP output stages in regulators. The PNP adds a LOT of gain to the feedback loop, something that an NPN stage does not do because an NPN stage acts as a voltage follower with gain equal to 1.
To fix the PNP or P MOS problem you have to look into compensating feedback loops, which may be a little more involved than you want to get into. For example, a Root Locus analysis would help to tell you what is going on.
Alternately, switch to an NPN or N MOS output stage which is a lot easier to deal with although it has to be driven properly to see the full output voltage.

 

Are you using the printed values or handwritten component values, especially for R13, R17 and C25?

R13= 0 ohm, R17 = 100 ohm, C25 = 10uF

 

R13= 0 ohm, R17 = 100 ohm, C25 = 10uF

Did you first try it with the printed component values?
If not, I would suggest that as a first step.

 

At 100 kHz, that isn't ripple. The circuit is unstable - an oscillator.

How much current is it supposed to handle?
What is the test current?
Have the FETs been precision matched for threshold voltage and transconductance?
Are the FETs very carefully mounted to make them all isothermal?

I would agreee with you that it is oscilating. its supposed to handle 3-5Amps or so, but right now im testing with a very light load, 500ma or so. I cant say that they have been carefully matched. The circuit is semi working. The FETs are definitely carefully mounted.

 

Did you first try it with the printed component values?
If not, I would suggest that as a first step.

I did, but it was oscillating even more.

 

Ok, so i was off on the frequency of the ripple. The input voltage is 62V right now. I sent you 4 screen shots, two with no load and the other 2 with 412 ohm load. The one with higher frequency ripple is with a load. Any ideas?

 

Is this a new design or something that has been known to work?

It has the look of a circuit designed for bipolar PNP transistors. There are ballast resistors of very low value in the FETs' sources. This is common in bipolar designs to improve sharing by producing local feedback or "degeneration" but does not work very effectively with power MOSFETs because of the comparatively low transconductance of FETs. My guess is that with unmatched FETs, one of them will be carrying almost all of the current. However, that isn't going to be important at this point because of the low current (at least I think it isn't - there is no DC safe operating area curve for the FETs in the schematic).

The circuit is oscillating because the loop gain is exactly 1.0 at a frequency that results in a phase shift around the loop of exactly 360 degrees. In order to fix this, it is necessary to change the gain and/or reduce the phase shift. Usually what you want to do is reduce the total phase shift to something a bit less that 300 degrees the highest frequency you can achieve as the gain passes through 0 dB while it is falling with a slope of -20 dB per decade (you don't strictly require this "minus one" slope, but it is much more difficult to assure the phase margin with steeper slope such as -40 dB per decade, called "minus two"). If you can make that happen you will have a circuit that responds quickly to changes in input voltage or output load without serious undershoot or overshoot and doesn't oscillate. If you can do it with very high loop gain at DC, which is usually possible, the DC regulation accuracy will be very good. It can be difficult to accomplish because you need to know how the circuit behaves open-loop to know how to close the loop to meet the objectives. Simulation, provided the device models are good, can be extremely helpful. Alternatively, actually trying to measure the gain and phase of the power path is nearly a necessity (typically you think of this sort of thing as being two parts: [the power path consisting of the FETs, the output capacitors and the load] and the error amplifier; in this case there is that bipolar driver in the middle with two poles deliberately added).

I suspect you will find that the op amp is actually producing a fairly large amplitude squarish output, possibly slamming rail to rail. It is run completely open loop, so its gain and phase response are simply its "natural" behavior. It is common to run an error amplifier open-loop at DC, but not AC.

I'm guessing the output capacitors are ceramic. What type are they? (some ceramics have a huge negative temperature coefficient of capacitance)

 

Just saw your waveforms. It looks to me like the FETs simply turn on very hard causing overshoot, then turn off completely allowing the output voltage to drop as a simple RC discharge.

 

Yes, this is a new design. I am a bit confused with your explanation, not that you said anything incorrect, just that I am not a subject matter expert. Any way you can clarify in simpler terms. Any recommendation based on what you see in screen captures?

 

If it's a new design, how come it's printed on old blue-line blueprint paper?

As ebp noted, that circuit will not work well, as one MOSFET will tend to hog all the current unless the MOSFETs all have their Vgs(th) voltages matched.

And the added gain of both Q6 and the MOSFETs are what's causing the oscillations.
It needs added compensation to maintain stability.
You could try increasing the value of C25.

What is the maximum output current?

I suggest a complete redesign.

 

Built this circuit on a PCB, but it is not regulating properly. It is set to regulate at 48V output (at 50V to 100V input). There is about a +/- 10 Volt swing at the output that looks like a ramp. How can this circuit be improved so that there is a 48V output of no more than a 500mV ripple and not a 10V ripple? Please help!

I think the fundamental issue here is the parallel PFETS: remember in order to make this voltage regulator working, the NPN and PFET operate at linear region. With multiple PFET, how can each PFET works with only one NPN. This is the reason you see output oscillation.

 

So I have removed R2, R4, R6 to disable Q1, Q2, and Q3 and not have any Pfet in parallel. I also increased C25 to 10uF. The problem is still there. Now it only runs for 20 seconds or so and stops regulating. Crutshow, since boards are already made, what changes would you recommend so I could jumper-in changes so I do not do a board redesign? I want it to output 5 amps or so.

 

It isn't easy to simplify.

Based on the waveforms (numbered for ease of reference):

1. the error amplifier (the op amp) "commands" the FETs to increase conduction to raise the output voltage
2. with light load, the FETs only have to be enhanced slightly to deliver sufficient current to meet the load requirement, but also adding charge to the output capacitors at the same time IF the voltage is allowed to rise
   
3. the error amplifier detects that the voltage has reached the setpoint and because it is fast and high gain it very rapidly commands reduction in the FET conduction, but ...
4. there are delays (delay in the time domain = phase lag in the frequency domain) in the circuit due to at least three separate RC circuits - R17 and C25, R13 and C19, and R13 and the capacitances of the FETs' gates so ...
5. the error amp has long since commanded reduction in the FET current, probably swinging its output to zero, but the delays prevent this from getting through to the FETs in time, so now you get gross overshoot of the setpoint
6. the error amp's output is now unquestionably sitting at the lowest voltage it can - the error amp is overdriven and acting as a comparator, which is a bad thing because that slows down its recovery to normal amplifying (but probably not really much a contributor here because other delays will be much larger)
7. the FETs respond and turn off completely (the actual response time can't be resolved at the time scales used)
8. slowly the overcharged output capacitors discharge through the load resistor and the voltage sense resistor chain
9. when the caps are sufficiently discharged the error amp's output will begin to rise to get the FETs to conduct again, but those same delays will come into play again and the voltage will probably drop to slightly below the set point
10. the error amp will now probably switch to having its output as high as it can go
11. the whole thing repeats

Each of those mentioned RC circuits introduces a time delay or "pole" in the response. There are two ways to deal with this (other than by eliminating unwanted poles where possible):

• make the frequency of one pole very low so that the gain of the loop drops to unity at a very low frequency. This can make the loop stable but very unresponsive - if there is a change in input voltage or output load it can take a long time for the circuit to repond
• compensate the poles by adding "zeros" which (on their own) cause phase "lead". Properly done this can result in good dynamic performance without oscillation or serious undershoot or overshoot problems

Again, the object is to make the overall gain of the closed loop pass through 0 dB "unity" (on its way down) with a total phase shift around the loop of no more than about 300 at that crossover frequency. This give 60 degrees of "phase margin" which results in pretty decent performance. If you get the loop frequency response set optimally, the slope of gain versus frequency for at least a decade or so below the crossover frequency would preferably be -20 dB per decade (-6 dB per octave). This slope also means that things that might mess with the crossover frequency are less likely to cancel that important 60 degrees of phase margin. The circuit won't oscillate with very low phase margin, but the dynamics will be poor with overshoots and undershoots.

One way to put a single zero into the response is to put a capacitor across R11. Try some smallish values of a few nanofarads to tens of nanofarads. Don't expect this to fix the problem, but you should see a change in behavior.

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Paralleling the FETs has nothing whatever to do with the behavior at the frequencies seen. There are lots of issues with paralleling, but the low frequency oscillation isn't one of them.

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If you are really lucky, Crutschow might simulate the circuit for you. If he does, be very grateful, because it will have taken quite a lot of work on his part.

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Using 0.1% tolerance resistors with an ordinary zener diode as the voltage reference is a waste of money.

 

So I have removed R2, R4, R6 to disable Q1, Q2, and Q3 and not have any Pfet in parallel. I also increased C25 to 10uF. The problem is still there. Now it only runs for 20 seconds or so and stops regulating. Crutshow, since boards are already made, what changes would you recommend so I could jumper-in changes so I do not do a board redesign? I want it to output 5 amps or so.

I think I know what the issue here is. You need a feed back network from invert pin to the output. Without this, the system will be unstable. Also you need to run stability simulation to ensure the feedback network is right configuration because you need to ensure the network has enough bandwidth to cover the load variation.