I am wondering about the BJT emitter voltage, refer to the green markers in the following simulate circuit.The other screenshot is the simulation result.
It seems like both FET and BJT worked in cut-off region, why there's a large voltage drop at emitter?

 

Hi Teddy,
With +11.82V on the Base and +16.37V on the Emitter it is reversed Biassed Off, not a voltage drop.
E

 

Hi T,
This is what I see with LTSpice, used an equivalent NMOS model
E

 

Hi Teddy,
With +11.82V on the Base and +16.37V on the Emitter it is reversed Biassed Off, not a voltage drop.
E

Hi Eric,
Thanks for explaining. I am still confuse about how it generate +16.37V, because the VGS of FET seems like smaller than it's Vth all the time and I think FET is always turn off.
Teddy

 

Hi T,
If you have 16.25V on adp pin, I get the same as you for those voltages.
E

Update:
What is adp connected too?

 

Hi T,
If you have 16.25V on adp pin, I get the same as you for those voltages.
E
View attachment 303581

Hi E,
The voltage I gave to the gate of FET is a pulse voltage source which VH=9.9V and VL=4.5V.
Teddy

 

Hi T.
This is with Gate pulse +4.5/9.9v
E

 

I am wondering about the BJT emitter voltage, refer to the green markers in the following simulate circuit.The other screenshot is the simulation result.
It seems like both FET and BJT worked in cut-off region, why there's a large voltage drop at emitter?

Hi E,
Sorry for that the drain voltage of FET should be 28V, here's the new circuit and the simulation result.
But I still confused how it generate +25.245V at VE while the VG equals to 4.5V.
Teddy

 

hi T,
What is the function of the circuit?
E

 

hi T,
What is the function of the circuit?
E

Hi E,
The function of this circuit is to transfer 28V from the adapter to 5-20V for PD controller. It use the voltage at VE to be the voltage for PD.
I am wondering it will generate the voltage between 5-20V based on the design, so I simulate the circuit.

 

Hi T,
OK,
You mean the pda voltage is an output voltage, so why have you got 28V connected to that pda point?
I would expect the PD controller to be connected as the Load for the pda signal.

E

Update:
Checking your circuit, the basic design is incorrect.

Is this a College or Homework assignment? Moderation.

 

Hi T,
OK,
You mean the pda voltage is an output voltage, so why have you got 28V connected to that pda point?
I would expect the PD controller to be connected as the Load for the pda signal.

E

Hi E,
I want to confirm the "pda voltage" you said is the voltage of emitter? Besides, you mean the circuit should look like the following circuit?

 

Hi T.
Checking your circuit, the basic design is incorrect, when using an NMOS FET with those Source and Gate voltages

Is this a College or Homework assignment? Moderation.

 

Hi T.
Checking your circuit, the basic design is incorrect, when using an NMOS FET with those Source and Gate voltages

Is this a College or Homework assignment? Moderation.

Hi E,
This is College assignment my friends asked me for help. I agree with what you said. It seems like the design is wrong, but it can simulate.

 

hi T,
Look at this clip from the datasheet,
To turn On the NMOS FET the Gate voltage has to be at least +1.3V with respect to the Source.

With a Source voltage of 28V, and the Gate with a +4.5v or 9.9V, it can never turn ON.

E

 

hi T,
Look at this clip from the datasheet,
To turn On the NMOS FET the Gate voltage has to be at least +1.3V with respect to the Source.

With a Source voltage of 28V, and the Gate with a +4.5v or 9.9V, it can never turn ON.

E
View attachment 303587

Hi E,
I agree. I tried to place a resistor(suppose it's load) and connected to emitter, refer to the following circuit. The simulate result seems make sense.


Teddy

 

hi T,
For the BC847B at 84mA with approx 21V, Collector to Emitter voltage is 0.084A *21V =1.75Watts, it will cook!
It's rated at 200 milliWatts.

E

 

hi T,
For the BC847B at 84mA with approx 21V, Collector to Emitter voltage is 0.084A *21V =1.75Watts, it will cook!
It's rated at 200 milliWatts.

E
View attachment 303591

Hi E,
Thanks for reminding, I'll communicate with my friend to see whether there is a better design. I really appreciate your support.
Teddy

 

Hi T,
As this is a College assignment, I cannot give a working simulation.

E

 

I am wondering about the BJT emitter voltage, refer to the green markers in the following simulate circuit.The other screenshot is the simulation result.
It seems like both FET and BJT worked in cut-off region, why there's a large voltage drop at emitter?

View attachment 303577

View attachment 303578

Look at the currents on those lines -- they are in the range of 20 pA. That includes the gate pin of the FET.

These are leakage currents in these devices. The node connected between the BJT and the FET is, ideally, a charge-storage node and is essentially floating. The voltage that appears on it is the result of a load-line balance between the leakage current characteristics of the connected devices.