Hey guys, we were being shown how to use if statements in vhdl and i cannot get it to work! Also my lecturer hasnt bothered to reply to my question regarding this so i would like to know what i am doing wrong before the exam.
This code compiles ok when the if statement is removed.
Thanks for the help!

When i try to analyse the code below with quartus II it says the folowing:


Error (10500): VHDL syntax error at demux4-to-16.vhd(16) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at demux4-to-16.vhd(36) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error: Quartus II Analyze Current File was unsuccessful. 2 errors, 0 warnings
Info: Allocated 190 megabytes of memory during processing
Error: Processing ended: Fri Dec 14 12:27:01 2007
Error: Elapsed time: 00:00:01

The code i wrote was for a demultiplexer model:

library IEEE;
use IEEE_std_logic_1164.all;
-- the above two lines instructs the program to use the two standard librabries

entity demux is
port( sel: in_std_logic_vector ( 3 downto 0 );
din: in_std_logic;
enable , ebar : in_std_logic;
dout: in_std_logic_vector ( 15 downto 0));

end demux;

architecture behaviour of demux is

begin
if enable = '1' and ebar = '0' then

dout <= "1111111111111110" when sel = "0000" else
"1111111111111101" when sel = "0001" else
"1111111111111011" when sel = "0010" else
"1111111111110111" when sel = "0011" else
"1111111111101111" when sel = "0100" else
"1111111111011110" when sel = "0101" else
"1111111110111110" when sel = "0110" else
"1111111101111110" when sel = "0111" else
"1111111011111110" when sel = "1000" else
"1111110111111110" when sel = "1001" else
"1111101111111110" when sel = "1010" else
"1111011111111110" when sel = "1011" else
"1110111111111110" when sel = "1100" else
"1101111111111110" when sel = "1101" else
"1011111111111110" when sel = "1110" else
"0111111111111110" when sel = "1111";


end if dout <= "1111111111111111";

end behaviour;

 

http://esd.cs.ucr.edu/labs/tutorial/

if ((enable = '1') and (ebar = '0')) then

I've never used that language but the code snipped from here suggests this format. I think end if needs to be on a separate line.

http://esd.cs.ucr.edu/labs/tutorial/AND_gate.vhd

architecture behav1 of AND_ent is
begin

process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;

end behav1;

 

Oh and you might look at the case statement on that dout block.

 

hi thanks alot for that, i will give that code a shot tonight and let you know if it worked.

 

Ok i tried what you said and quartus II is still complaining. The relevent altered code is here:

begin
if ((enable = '1') and (ebar = '0')) then

dout <= "1111111111111110" when sel = "0000" else
"1111111111111101" when sel = "0001" else
"1111111111111011" when sel = "0010" else
"1111111111110111" when sel = "0011" else
"1111111111101111" when sel = "0100" else
"1111111111011110" when sel = "0101" else
"1111111110111110" when sel = "0110" else
"1111111101111110" when sel = "0111" else
"1111111011111110" when sel = "1000" else
"1111110111111110" when sel = "1001" else
"1111101111111110" when sel = "1010" else
"1111011111111110" when sel = "1011" else
"1110111111111110" when sel = "1100" else
"1101111111111110" when sel = "1101" else
"1011111111111110" when sel = "1110" else
"0111111111111110" when sel = "1111";


end if dout <= "1111111111111111";

end behaviour;

the errors it said are here:

Info: Running Quartus II Analyze Current File
Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
Info: Processing started: Sun Dec 16 12:48:32 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demux4-to-16 -c demux4-to-16 --analyze_file=C:\altera\72\quartus\demux4-10-16\demux4-to-16.vhd
Error (10500): VHDL syntax error at demux4-to-16.vhd(16) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at demux4-to-16.vhd(16) near text "then"; expecting "<="
Error (10500): VHDL syntax error at demux4-to-16.vhd(36) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Error: Quartus II Analyze Current File was unsuccessful. 3 errors, 0 warnings
Info: Allocated 190 megabytes of memory during processing
Error: Processing ended: Sun Dec 16 12:48:33 2007
Error: Elapsed time: 00:00:01

Not even my lecturer knows what the problem is hahahahaha

 

Have you tried using a process? I usually use those when doing 'if' statements. The beginning of the process may look something like:

process (enable, ebar)
if(...)
-
-
-
end if;
end process;