I am using Vivado:



The following timing is observed:



Notice data_ready goes high after the first 1200 ns.

The test bench for this is suppose to wait until data ready goes high and then proceeds to perform more actions via the following wait until in the test bench:



It never makes it past line 71. Apparently I am doing something wrong, as the timing diagram shows it going to logic '1' but the wait until statement does not seem to work the way I expected. Normally I use wait unit for the clock with no issues, something like this:

wait until rising_edge(clk);

That seems to work fine. Not sure what I am doing wrong here.

 

The issue turned out to be that the process being simulated is synchronized to the clock. The following fixes the issue, but I am not 100% why it does:

wait until rising_edge(clk) and data_ready='1';

 

It might be helpful to see the rest of your process (or at least any parameters). Is it sensitive to any signals?

 

It might be helpful to see the rest of your process (or at least any parameters). Is it sensitive to any signals?

Here is both the test bench and the rtl file. None of this is proprietary and is all public domain.
The UART_Transmitter is sensitive to the clk.

Thanks for your help!