hi i am trying to implement a fir filter that is in the paper that i attached its link below with vhdl . the problem is i cant find out what is inside the block diagrams in Figure3 .from section 3 in the paper it seems that we should use a state machine but i have some questions .
1- what is s(i) in state 1?
2- what should we do in state 3-6
3- what is tree shift adder i searched a lot but i couldn't find anything about it
thanks
http://ieeexplore.ieee.org/document/...6/?reload=true

 

hi hamid,
Welcome to AAC.
Your link requires that viewers need to have a IEEE or other recognised Institution Log in ID, in order to view the document.
E

 

hi hamid,
Welcome to AAC.
Your link requires that viewers need to have a IEEE or other recognised Institution Log in ID, in order to view the document.
E

ok i attached the pdf file of the required paper

 

i figured out how to implement shift register stage and ROM stage. but I'm stock at the tree shift adder stage . I implemented it from a block diagram from some other paper(i attached it ) and i attached my implementation too.
i have the following problems : 1-n stocks in 1 value and never changes .2- d should be 16 bits and ip1 and ip2 should be 32 bits but the multiplexer is supposed to put inputs directly into output according to sel. i tried to solve it by getting 16 bits of the inputs. is this way correct ?