VHDL testbench "entity does not match component" error

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esperanzam

Joined Apr 6, 2017
1
I have a vhdl code written for a shifter made with d-flip flops and multiplexers which runs and checks with successful syntax. However, now that i'm working on the testbench i'm running into some errors. The errors state that the entity does not match the component port for "clk", "il", "ir", "i", "s", and "q". I have researched the answer and so far the suggestions were to change the library from ieee.std_logic_arith.ALL to ieee.std_logic_numberic.ALL however, although I already have the ieee.std_logic_numberic.ALL library I keep getting the same errors.


The VHDL Code is:


Code:
LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
PORT(i3, i2, i1, i0 :INBIT;
s:INBIT_VECTOR(1DOWNTO0);
o:OUTBIT); 
END MUX41;

ARCHITECTURE arch_mux41 OF MUX41 IS
BEGIN PROCESS (i3, i2, i1, i0, s) BEGIN CASE s IS 
WHEN "00"=> o <= i0; 
WHEN "01"=> o <= i1;
WHEN "10"=> o <= i2;
WHEN "11"=> o <= i3; 
WHEN OTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END arch_mux41;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF IS
PORT(d, clk :INBIT;
q, qb :OUTBIT);
END DFF;
ARCHITECTURE arch_dff OF DFF IS
BEGIN PROCESS (clk) VARIABLE q_temp :BIT;BEGINIF(clk'EVENTAND clk='1')THEN
q_temp := d;
ENDIF;
q <= q_temp;
qb <=NOT q_temp;
ENDPROCESS;
END arch_dff;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY UShift IS
PORT(clk, il, ir :INBIT;
s:INBIT_VECTOR(1DOWNTO0);
i :INBIT_VECTOR(3DOWNTO0);
q :OUTBIT_VECTOR(3DOWNTO0));
END UShift;

ARCHITECTURE struct OF UShift IS
COMPONENT MUX41
PORT(i3, i2, i1, i0 :INBIT;
s:INBIT_VECTOR(1DOWNTO0);
o:OUTBIT);
ENDCOMPONENT;[/SIZE]

[SIZE=3]COMPONENT DFF PORT(d, clk :INBIT;
q, qb :OUTBIT);ENDCOMPONENT;[/SIZE]

[SIZE=3]FOR U1, U2, U3, U4: MUX41 USE ENTITY WORK.MUX41(arch_mux41);
FOR U5, U6, U7, U8: DFF USE ENTITY WORK.DFF(arch_dff);
SIGNAL o:BIT_VECTOR(3DOWNTO0); 
SIGNAL qb:BIT_VECTOR(3DOWNTO0); 
SIGNAL qt:BIT_VECTOR(3DOWNTO0);
BEGIN
U1:MUX41 PORTMAP(il,qt(2), i(3), qt(3), s, o(3));
U2:MUX41 PORTMAP(qt(3), qt(1), i(2), qt(2), s, o(2));
U3:MUX41 PORTMAP(qt(2), qt(0), i(1), qt(1), s, o(1));
U4:MUX41 PORTMAP(qt(1), ir, i(0), qt(0), s, o(0));
U5:  DFF PORTMAP(o(3), clk, qt(3), qb(3));
U6:  DFF PORTMAP(o(2), clk, qt(2), qb(2));
U7:  DFF PORTMAP(o(1), clk, qt(1), qb(1));
U8:  DFF PORTMAP(o(0), clk, qt(0), qb(0));
q <= qt;
END struct;

The testbench is:


Code:
LIBRARY ieee; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL;[/SIZE]

[SIZE=3]ENTITY UShift_test IS
END UShift_test;[/SIZE]

[SIZE=3]ARCHITECTURE behavior OF UShift_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UShift 
PORT(clk :IN std_logic; il :IN std_logic; ir :IN std_logic; i :IN std_logic_vector(3downto0); s:IN std_logic_vector(1downto0);
q :OUT std_logic_vector(3downto0)); ENDCOMPONENT;[/SIZE]

[SIZE=3]--Inputssignal 
clk :std_logic:='0';
signal il :std_logic:='0';
signal ir :std_logic:='0';
signal s :std_logic_vector(1downto0):=(others=>'0');
signal i :std_logic_vector(3downto0):=(others=>'0');
--Outputssignal 
q :std_logic_vector(3downto0);   
-- Clock period definitions
constant clk_period :time:=20 ns;[/SIZE]

[SIZE=3]BEGIN-- Instantiate the Unit Under Test (UUT)
uut: UShift PORTMAP(
clk => clk,
il => il,
ir => ir,
s => s,
i => i,
q => q);[/SIZE]

[SIZE=3]-- Clock process definitions
clk_process:  process
begin
clk <='0';waitfor clk_period/2;
clk <='1';waitfor clk_period/2; endprocess;[/SIZE]

[SIZE=3]-- Stimulus process
stim_proc:  process 
begin

---- test clr
ir<='0';
wait for 40 ns;

---- test parallel loading
ir<='1';
s<="11";
i<="0010";
wait for 40 ns;

---- test shift right
s<="01";
il<='1';
wait;
endprocess;
END;
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