Code:
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-- Company:
-- Engineer:
--
-- Create Date: 14:30:01 05/25/2015
-- Design Name:
-- Module Name: count - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count is
Port ( count : in STD_LOGIC_vector (1 downto 0);
reset : in STD_LOGIC ;
output : out STD_LOGIC_vector (1 downto 0);
clk : in STD_LOGIC);
end count;
architecture Behavioral of count is
signal y:STD_LOGIC_vector (1 downto 0);
begin
process ( reset , clk)
variable var: integer := 100;
begin
y <= count ;
l1: loop
exit l1 when var = 0 ;
if (reset='0') then
if (rising_edge(clk)) then
y <= y+"01";
var := var-1;
else
end if ;
output (1 downto 0) <= y (1 downto 0);
else
output (1 downto 0)<="00";
end if;
end loop;
end process;
end Behavioral;
is my program ok. plz someone ckeck , it is showing no syntax error however , but plz point the logicasl error if any . thank you.