# VHDL -Please check my code

#### payel

Joined Feb 10, 2015
5
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:30:01 05/25/2015
-- Design Name:
-- Module Name:    count - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count is
Port ( count  : in  STD_LOGIC_vector (1 downto 0);
reset  : in  STD_LOGIC ;
output : out  STD_LOGIC_vector (1 downto 0);
clk : in  STD_LOGIC);
end count;

architecture Behavioral of count is

signal y:STD_LOGIC_vector (1 downto 0);

begin
process ( reset , clk)

variable var: integer := 100;
begin

y <= count ;

l1: loop
exit l1 when var = 0 ;

if (reset='0') then
if (rising_edge(clk)) then

y <= y+"01";
var := var-1;

else

end if ;

output (1 downto 0) <= y (1 downto 0);

else
output (1 downto 0)<="00";
end if;

end loop;

end process;
end Behavioral;

is my program ok. plz someone ckeck , it is showing no syntax error however , but plz point the logicasl error if any . thank you.

#### kubeek

Joined Sep 20, 2005
5,733
How should we know? You didn´t provide any specification of what the code si supposed to do.

#### payel

Joined Feb 10, 2015
5
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:30:01 05/25/2015
-- Design Name:
-- Module Name:    count - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count is
Port (
reset  : in  STD_LOGIC ;
output : out  STD_LOGIC_vector (1 downto 0);
clk : in  STD_LOGIC);
end count;

architecture Behavioral of count is

begin
process ( reset , clk)

variable y:STD_LOGIC_vector (1 downto 0):= "00";

begin

if (reset='0') then
if (rising_edge(clk)) then

y := y+"01";

else

end if ;

output (1 downto 0) <= y (1 downto 0);

else
output (1 downto 0)<="00";
end if;

end process;
end Behavioral;
check this , ignore the above program.

o, ok sorry it is a 2 bit counter . where the initial value is provided "00" and then it will count 01, 10, 11 ,00 but b4 every count it will check reset and clk.

#### kubeek

Joined Sep 20, 2005
5,733
I have to say I used VHDL a long time ago, so I can´t really tell if the syntax is correct. Nevertheless the code looks correct, even though all the (1 downto 0) seem superfluous and not really needed. How did the simulation come out?

#### payel

Joined Feb 10, 2015
5
if i simply want to design a clock with a time period of some delay as given for each on and off period . then will my following code work.

Code:
begin
process
begin

a <= '1';

var := 5000;
while var >0 loop
var := var-1;
end loop;

a <= '0';

var := 5000;
while var >0 loop
var := var-1;
end loop;

end process ;

#### payel

Joined Feb 10, 2015
5
I have to say I used VHDL a long time ago, so I can´t really tell if the syntax is correct. Nevertheless the code looks correct, even though all the (1 downto 0) seem superfluous and not really needed. How did the simulation come out?

ok, 1stly the syntax is correct , i have compiled it . i want to know if there is any logical error bec i often confuse it with c /fortran. and another thing , plz say me how to start a new thread .

#### kubeek

Joined Sep 20, 2005
5,733
Go to http://forum.allaboutcircuits.com/forums/programmers-corner.12/ click Start new thread in the upper right corner, and please make sure to give the thread a good title that describes it for others. Something like VHDL counter should be ok.

Why do you think that code will produce 10ns clock? It could be be 10000 seconds period just as well. Or maybe nothing at all if you try to synthesize it.
If it is for simulation, why not try some wait statements or whatever its called in vhdl, instead of counting some illdefined iterations?

#### payel

Joined Feb 10, 2015
5
Go to http://forum.allaboutcircuits.com/forums/programmers-corner.12/ click Start new thread in the upper right corner, and please make sure to give the thread a good title that describes it for others. Something like VHDL counter should be ok.

Why do you think that code will produce 10ns clock? It could be be 10000 seconds period just as well. Or maybe nothing at all if you try to synthesize it.
If it is for simulation, why not try some wait statements or whatever its called in vhdl, instead of counting some illdefined iterations?

yes actually i have read process statement . there i have read that if the process has sensitivity list then signal assignment occurs only when all the statements of the process get executed . but if it has no ensitivity list then we need to give a wait statement after every signal assignment . but wait is not synthesizable. then what do we need to do or give in place of wait statement .

say for eg:

begin

process

begin

a <= '1';

wait for 10 ns;

a<='0';

wait for 10 ns;

here a is firstly assigned with '1' and thenm with '0' . but wait statement is not synthesizable , so in place of wait what do i need to give so that firstly '1' is sent to a port c of fpga and then '0' is sent to the same port of fpga . can we use a delay in place of wait . for eg:

begin
process
begin

a <= '1';

var := 5000;
while var >0 loop
var := var-1;
end loop;

a <= '0';

var := 5000;
while var >0 loop
var := var-1;
end loop;

end process ;

#### kubeek

Joined Sep 20, 2005
5,733
In synthesis you cannot generate something from nothing. Your chip will need a clock input coming from an external oscillator, then you base everything on that clock.

#### tshuck

Joined Oct 18, 2012
3,534
payel post: 864041 said:
but wait statement is not synthesizable
Not all implementations of the wait statement are synthesizable, though there are that can be.
A common way to do this is a process that is sensitive to clk and reset:
Code:
--entity declaration

architecture behavioral of <entity_name> is
signal internal_count : std_logic_vector (1 downto 0) := "00";
begin

--these are the same size, no need to specify their lengths
output <= internal_count;

counter_proc: process (clk, reset)
begin
if (reset = '1') then
--reset state
elsif (rising_edge (clk)) then
--increment count
end if;
end process;
end architecture;
A synthesizable wait statement uses slightly different syntax:
Code:
--entity declaration

architecture behavioral of <entity_name> is
signal internal_count : std_logic_vector (1 downto 0) := "00";
begin

--these are the same size, no need to specify their lengths
output <= internal_count;

counter_proc: process
begin
wait until clk='1' and clk'event;
if (reset = '0') then
--reset state
else
--increment count
end if;
end process;
end architecture;
This makes a synchronous reset however.

To make an asynchronous reset, you could do something more like:
Code:
--entity declaration

architecture behavioral of <entity_name> is
signal internal_count : std_logic_vector (1 downto 0) := "00";
begin

--these are the same size, no need to specify their lengths
output <= internal_count when reset = '1' else " 00";

counter_proc: process
begin
wait until clk='1' and clk'event;
--internal_count <= incremented value;
end process;
end architecture;
Hopefully this captures the idea without giving away too much.....

say for eg:

begin

process

begin

a <= '1';

wait for 10 ns;

a<='0';

wait for 10 ns;
The "wait for" form is not synthesizable, at least, not generally, though there may be synthesis tools that will, knowing what frequency a master clock is at, inner the logic required to generate those timings in the wait statements, though I wouldn't count on these existing.

The 'wait for' is usually used in testbench writing to verify a synthesizable design before going into any hardware.

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