Hello
I have written a small program in vhdl for practice purpose but i am getting some error like below.Not able to solve the problem
Parsing architecture <Behavioral> of entity <test1>.
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 40: Syntax error near "process".
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 42: Syntax error near "then".
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 44: Syntax error near "if".
VHDL file D:\Others\Project\XilingProgramm\test1\test1.vhd ignored due to errors
I have written a small program in vhdl for practice purpose but i am getting some error like below.Not able to solve the problem
Parsing architecture <Behavioral> of entity <test1>.
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 40: Syntax error near "process".
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 42: Syntax error near "then".
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 44: Syntax error near "if".
VHDL file D:\Others\Project\XilingProgramm\test1\test1.vhd ignored due to errors
Rich (BB code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test1 is
Port ( clk : in STD_LOGIC;
input1 : in STD_LOGIC;
input2 : in STD_LOGIC;
output : out STD_LOGIC);
end test1;
architecture Behavioral of test1 is
process(clk)
begin
if (clk'event and clk='1') then
output <= input1 and input2;
end if;
end process;
end Behavioral;