Vhdl Error

Thread Starter

Rockyy

Joined Jul 10, 2014
7
Hello

I have written a small program in vhdl for practice purpose but i am getting some error like below.Not able to solve the problem

Parsing architecture <Behavioral> of entity <test1>.
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 40: Syntax error near "process".
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 42: Syntax error near "then".
ERROR:HDLCompiler:806 - "D:\Others\Project\XilingProgramm\test1\test1.vhd" Line 44: Syntax error near "if".
VHDL file D:\Others\Project\XilingProgramm\test1\test1.vhd ignored due to errors
Rich (BB code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test1 is
    Port ( clk : in  STD_LOGIC;
           input1 : in  STD_LOGIC;
           input2 : in  STD_LOGIC;
           output : out  STD_LOGIC);
end test1;

architecture Behavioral of test1 is
  process(clk)
begin
      if (clk'event and clk='1') then
        output <= input1 and input2;
        end if;
end process;

end Behavioral;
 

Thread Starter

Rockyy

Joined Jul 10, 2014
7
For the above Program I have created a VHDL test bench like below

Rich (BB code):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test IS
END test;
 
ARCHITECTURE behavior OF test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT test1
    PORT(
         clk : IN  std_logic;
         input1 : IN  std_logic;
         input2 : IN  std_logic;
         output : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal input1 : std_logic := '0';
   signal input2 : std_logic := '0';

     --Outputs
   signal output : std_logic;

   -- Clock period definitions
   constant clk_period : time := 1 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: test1 PORT MAP (
          clk => clk,
          input1 => input1,
          input2 => input2,
          output => output
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 10 ns;     
        input1 <= '0';
        input2 <= '0';
        
        wait for 20 ns;
        input1 <= '0';
        input2 <= '1';
        
        wait for 30 ns;
        input1 <= '1';
        input2 <= '0';
        
        wait for 40 ns;
        input1 <= '1';
        input2 <= '1';

    
   end process;

END;
but after simulating the behavioural Model i am getting the value of
clk = U
input1 = U
input2 = U
output = U
 

Attachments

Brownout

Joined Jan 10, 2012
2,390
I made a simple change to your clock and it works. However, as you have written the test bench, there is no end, so the simulation goes on forever.


Rich (BB code):
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 
 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
 --USE ieee.numeric_std.ALL;
 
 ENTITY test IS
 END test;
 
 ARCHITECTURE behavior OF test IS 
 
 -- Component Declaration for the Unit Under Test (UUT)
 
 COMPONENT test1
 PORT(
 clk : IN std_logic;
 input1 : IN std_logic;
 input2 : IN std_logic;
 output : OUT std_logic
 );
 END COMPONENT;
 
 --Inputs
 signal clk : std_logic := '0';
 signal input1 : std_logic := '0';
 signal input2 : std_logic := '0';
 --Outputs
 signal output : std_logic;
 -- Clock period definitions
 constant clk_period : time := 1 ns;
 
 BEGIN
 
 -- Instantiate the Unit Under Test (UUT)
 uut: test1 PORT MAP (
 clk => clk,
 input1 => input1,
 input2 => input2,
 output => output
 );
 -- Clock process definitions
 clk <= NOT clk after 1ns;
 -- Stimulus process
 stim_proc: process
 begin 
 -- hold reset state for 100 ns.
 wait for 10 ns; 
 input1 <= '0';
 input2 <= '0';
 
 wait for 20 ns;
 input1 <= '0';
 input2 <= '1';
 
 wait for 30 ns;
 input1 <= '1';
 input2 <= '0';
 
 wait for 40 ns;
 input1 <= '1';
 input2 <= '1';
 
 end process;
 END;
 

Attachments

Top