VGSmax/VGSS specification whether it applies to Maximum VGD voltage possible in Circuit

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Hi,

I am planning to use DMN2005 MOSFET in one of our designs. It is used at multiple places.
In one part of the circuit, it is used as part of simple inverter.
Drain is connected to a supply Vsc = Typ 12V, worst peak 15V with pull-up resister of 10K.
Source is GND. Gate has 1K pulldown and driven by controller which can output 3.3V or 0V.

Now my doubt,
The max Vgs will be 3.3V
max Vds will be 15V
Max Vgd will be -15V.

Whether the spec Max VGS /VGSS(for DMN2005 it is +/- 10V) from the datasheet can be used to verify Max VGD(-15V) in the circuit.
If we can't use that specification(VGSS/Max VGS), Is there any specification in the datasheet which can be used to check this VGD max in the circuit.
 

Ian0

Joined Aug 7, 2020
1,628
Vgd(max) is about the same as Vds(max).
If you think about how to make a MOSFET the gate and source are on the top and the drain is on the bottom.
 

Ian0

Joined Aug 7, 2020
1,628
Are you trying to tell me that a 1200V MOSFET is limited to 20V between gate and drain?

The oxide is between the gate and the source. The drain connection is on the other side of the wafer.
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Vgd(max) is about the same as Vds(max).
If you think about how to make a MOSFET the gate and source are on the top and the drain is on the bottom.
Hi Ian,

I was under impression that VGSmax/VGSS is the gate oxide breakdown voltage which is common between Gate,Source or Gate,Drain. But you are saying the construction of the MOSFET is different (Drain is on Top, Gate,Source are in Bottom of the package).
How can we check whether a MOSFET withstands the worst case voltage across VGD. i mean to check Max Vgs of the design we have VGSmax/VGSS & to check Max Vds in design we have VDSS/VDS max - Is there any spec for Max VGD or can we imply something from VGSmax & VDSmax specifications
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Are you trying to tell me that a 1200V MOSFET is limited to 20V between gate and drain?

The oxide is between the gate and the source. The drain connection is on the other side of the wafer.
Thanks Ian,
So, i no need to worry about Max VGD voltage w.r.t VGS max specification - Because Gate oxide layer between Gate to Drain is thick or they are very apart.

So, in actual circuit,
If we verify Max VGS of the circuit< VGSS/VGS max of datasheet and
VDS max of the circuit < VDSS/VDS max of the datasheet
are we fine or is there any need to verify VGD max of the circuit also with any of the datasheet parameter.
Can we deduct VGDmax = VGSmax(datasheet spec)-VDSmax(datasheet spec)
 

dl324

Joined Mar 30, 2015
12,684
Most MOSFETs are going to be constructed with the drain and source on the same side of the silicon. So maximum Vgs and Vgd will be the same.

From Wikipedia:
clipimage.jpg

Some power devices use different topologies. Unless you know you're not working with the former, use the maximum Vgs to also mean Vgd.
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Most MOSFETs are going to be constructed with the drain and source on the same side of the silicon. So maximum Vgs and Vgd will be the same.

From Wikipedia:
View attachment 220983

Some power devices use different topologies. Unless you know you're not working with the former, use the maximum Vgs to also mean Vgd.
Thanks dl324,
I am under the same impression.
I see one catch here is If we see the datasheet of DMN2005 we have Drain terminal on other side and Gate & Source are in same side, --> distance between gate to source is small compared to Distance between Gate to Drain , even though i am not sure what is actually on the wafer side.

The diagram you shared - are you sure it will represent DMN2005's internal construction
IN our text books , i see gate to source and gate to drain voltages are equally important in developing field & for forming inversion region.
 

dl324

Joined Mar 30, 2015
12,684
I see one catch here is If we see the datasheet of DMN2005 we have Drain terminal on other side and Gate & Source are in same side, --> distance between gate to source is small compared to Distance between Gate to Drain , even though i am not sure what is actually on the wafer side.
There is no correlation between pin order on the package and how the device is constructed.
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Hi Ian0,
as per dl324 there is no correlation between pin order and the construction. Do you have any comment on the construction of this ic.
I will ask ti also on the construction data.
 

Ian0

Joined Aug 7, 2020
1,628
1. The biggest clue is in the datasheet. Take the extreme example of the 1200V MOSFET (Vds(max) =1200V, Vgs(max) = +/-20V)
If the gate is at -20V, the device is OFF and the drain is at +1200V. Therefore, the voltage between gate and drain is 1220V.
If that were not the case, what voltage COULD you put on the gate?
2. This is the construction of a modern power MOSFET. (Wikipedia shows a stylised lateral MOSFET). The drain is on one side and is soldered to the package for heat dissipation, the gate and source are on the top, separated by the oxide.
3. There IS a correlation between pin order and construction. On all the metal tab packages, the tab is soldered to the die, and the side of the die that is soldered is always the drain. (The only exception is the few lateral power MOSFETs descended from Hitachi 2SK134, that are used in specialised linear applications)
 

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Bordodynov

Joined May 20, 2015
2,806
Due to the presence of an epitaxial layer, the structure takes the form of n- and n+. The epitaxial region n- is part of a field-effect transistor with a pn-junction. That is, the transistor is a connection of two transistors in series. When the lower MOS transistor is closed, almost all voltage drops to jfet (at least part of it). As a result the transistor jfet cut-off voltage (<10 V) is applied to the sub-gate oxide. If there was no epitaxial region, your fears would be justified.
 

Ian0

Joined Aug 7, 2020
1,628
Due to the presence of an epitaxial layer, the structure takes the form of n- and n+. The epitaxial region n- is part of a field-effect transistor with a pn-junction. That is, the transistor is a connection of two transistors in series. When the lower MOS transistor is closed, almost all voltage drops to jfet (at least part of it). As a result the transistor jfet cut-off voltage (<10 V) is applied to the sub-gate oxide. If there was no epitaxial region, your fears would be justified.
You must have done your semiconductor physics more recently than I did. Which bit forms the gate of the jfet?
 

Thread Starter

malli_1729

Joined Nov 28, 2012
26
Thanks guys,
Here, is the TI's explanation for similar question on different MOSFET.
"The internal geometry of the gate's position with respect to both the drain and source dictate that the most stress will be absorbed from gate to source, not gate to drain. In other words, the max Vgd is not the same as the max Vgs, and is much greater such that the max Vgs or max Vds will always be exceeded first. "

from this we are safe to operate this device even though VGD goes to -15V.

But one doubt,
Ian0,
IF we see the dimensions from package, Gate to Source clearance is 0.2mm, Drain to Source Clearance is 0.4mm, as crude approx i felt VGDMax can't be > 2*VGSmax. Some how i didn't understand the physics behind/logic behind statement " first Max VDS/VGS will exceed before VGD"
 

Bordodynov

Joined May 20, 2015
2,806
And we made CMOS microcircuits with thickness of sub-gate oxide 0.1 µm. So it broke through at 90 volts. n-channel transistor was broken through at 30 V, and p-channel transistor was broken through at 50 V (at long channel ~ 20 µm, working length of channel is 5 µm). Transistors had horizontal structure.
 
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