Hi all.
I really need help with Verilog.
Our lecturer has restricted to use if/else and etc.. We are allowed to use just AND OR NOT and etc logic gates.
We are also restricted to use counters like n = n + 1 and supposed to make it with flip-flops
Deadline: August 22, 2014 (11:59pm)
The Prime Number
A prime number (or a prime) is a natural number greater than 1 that has
no positive divisors other than 1 and itself. A natural number greater than
1 that is not a prime number is called a composite number. For example, 5
is prime because 1 and 5 are its only positive integer factors, whereas 6 is
composite because it has the divisors 2 and 3 in addition to 1 and 6.
In this assignment, on the Verilog environment, you will design a prime
counter counting between 1-63 and repeating 5 times by returning to the
beginning. Your each code line must include an explanation line, and another
something important is that your codes must be synthesizable.
Im stuck at making counters because dont know Verilog well
My code is:
I cant even test my flip flop...
I really need help with Verilog.
Our lecturer has restricted to use if/else and etc.. We are allowed to use just AND OR NOT and etc logic gates.
We are also restricted to use counters like n = n + 1 and supposed to make it with flip-flops
Deadline: August 22, 2014 (11:59pm)
The Prime Number
A prime number (or a prime) is a natural number greater than 1 that has
no positive divisors other than 1 and itself. A natural number greater than
1 that is not a prime number is called a composite number. For example, 5
is prime because 1 and 5 are its only positive integer factors, whereas 6 is
composite because it has the divisors 2 and 3 in addition to 1 and 6.
In this assignment, on the Verilog environment, you will design a prime
counter counting between 1-63 and repeating 5 times by returning to the
beginning. Your each code line must include an explanation line, and another
something important is that your codes must be synthesizable.
Im stuck at making counters because dont know Verilog well
My code is:
Rich (BB code):
module dff (Q,D, CK);
input CK,D;
output Q;
wire NM,NCK;
wire NQ,M;
nand DN1 (NM,D,CK);
nand DN2 (M,NM,CK);
nand DN3 (Q,NQ,NM);
nand ND4 (QN,Q,M);
endmodule
module tb;
reg D, CK;
wire Q;
dff p0(Q, D, CK);
//jkstruct m0(q, qn, t, cp);
initial begin
D = 0;
CK = 1;
#100;
$display(Q);
D = 0;
CK = 1;
#50
$display(Q);
D = 1;
CK = 0;
#50
$display(Q);
D = 1;
CK = 1;
$display(Q);
$finish;
end
endmodule
I cant even test my flip flop...