This section is intended to supplement the section already present on synchronous counters and immediately follow it. This is meant to formalize the process of sequential logic design as applies to counters, using many techniques used in subsequent sections, namely modulus counters(which I will post for review shortly), and finite state machines.
Again, let me know if anything is wrong or if you think it can be improved(and I will debate you).
Thanks for taking the time to give it a read through!
Again, let me know if anything is wrong or if you think it can be improved(and I will debate you).
Thanks for taking the time to give it a read through!
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