# Submission: Counter modulus

## What did you think?

• ### Didn't read it, couldn't be bothered

• Total voters
7

#### tshuck

Joined Oct 18, 2012
3,534
So, it seems like I've been cranking these things, out, but really I made the counter modulus and the synchronous counter design section at the same time, so it's more like finishing one section. I just wanted to take some more time to review the counter modulus as there's a lot more content.

So, this is the counter modulus, intended to take place where is currently is in the e-book.

Again, please leave comments/concerns/quips/gripes/and funny pictures if you'd like. Let me know if you've read the article so that we can at least say this thing is being reviewed, which can be as simple as voting in the poll on this thread.

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#### tshuck

Joined Oct 18, 2012
3,534
Counter modulus

Every counter has a number of states it represents, this number is referred to as the counter's modulus.

So far we have looked at counters that count up to the maximum number of possible states for flip flops. The previous section saw a counter using four flip flops, allowing a count from 0 to 15, with 16 individual states represented by the counter. This makes the counter a modulus 16 counter, or a Mod-16 counter. No matter what number of times we allow the counter to count, by applying clock pulses, it will be somewhere with a value of 0 to 15.

Now, what happens if we do not want to use all the possible states for the flip flops? To introduce the topic, allow us to examine a very simple counter: the Mod-3 counter.

As the name implies, this counter will only have three states. Let us show them in a state table.

You will notice the last state, 11, is not accounted for in the count sequence, this is a don't care condition, meaning we may use the state to minimize our logic. It is important to note that the don't care can provide a source of error in a design, If we were to use both don't care conditions as 1, and the counter was to power up into state 11, it may never leave the state, unless power was taken away and re-applied. To circumvent this, one could make the count also go to 00 if ever the counter found itself at 11, for whatever reason. The trade-off is the amount of hardware used in the final product. Additionally, we could strike a compromise with minimal hardware and fault tolerance by only using the number of don't cares that would allow the counter to be put into a valid state. For now, allow us to assume the counter will never be in state 11, and design accordingly.
Let us then use the techniques learned to create the input forming logic. We shall examine this circuit using both JK and D type flip flops.

Using JK flip flops, we must define the input-forming logic for both J and K.

From the minimized input-forming logic, we can create our circuit:

Using D flip flops, we must only create the input-forming logic for the D input of each flip flop.

Again, from the minimized input-forming logic, we can create a circuit.

Both circuits realize the same function and will have the same timing diagram.

This circuit will count from 0 to 2 and repeat so long as there is a clock applied.

When designing with don't care conditions, it is important to provide a way for the system to correct itself, given enough time. If we had utilized both don't care states in the 11 state, it could present a problem: if the flip flops were powered up in the 11 state, it would never exit, remaining in the 11 state until power was cycled again. As is, if the system was to ever enter into the 11 state, the next state would be 10, exiting the invalid state, allowing for counting to resume.

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#### tshuck

Joined Oct 18, 2012
3,534
To further our understanding of the modulus counter, we will take a slightly more complex problem: a Mod-10 counter.

Modulus ten counting is decimal counting using only the units place: 0 to 9, then, roll over to 0.

Now we begin as before, we will create a state table.

As before, all valid states have a next state defined, and, in the case of the final count value, the next state is the initial count sequence, or 0, in this case. All other states outside of the count sequence are don't care states.

We will use JK flip flops to create this counter. So we will create Karnaugh maps for each flip flops J and K inputs.

From this we can create the circuit with the prescribed inputs on our flip flops.

The timing diagram for the Mod-10 counter is:

So, the Mod-10 counter works, we are done designing our circuit, however, to ensure our system is robust and fault tolerant, we need to see what happens when the flip flops come up in an invalid state for our counter.

The don't care states we used earlier in our input-forming logic minimization determine what the next state is for an invalid count. To determine where our counter goes from an invalid state, we need to examine our invalid states and where the count will go to next.
Invalid States:
• 1010
• 1011
• 1100
• 1101
• 1110
• 1111
Let us take state 1010, we will determine what the next count is, if ever the device finds itself in this state.

From the Karnaugh maps we made earlier to determine our input-forming logic, we can determine our next state. First, we will examine the most significant bit, as every count where Q3 = 0 is a valid state for our count sequence. If, however, Q3 turns out to be 1, there are only two valid states where Q3 = 1, 1000 and 1001. Examining what happens to Q3 when the state is 1010 from the Karnaugh map, Q3, the most significant bit of our count is 1. When a JK flip flop's output is 1, the output is determined by its K input, meaning the input K3 determines the next state of Q3.

Since we have not included the don't care state within the minimization grouping in the Karnaugh map for K3, it evaluates to a output of 0. Given the JK flip flop's characteristics, the next state for Q3, while K3 = 0, is the current state of Q3, or 1.

Since the next state could be an invalid state, we must progress to Q2, the next-most significant bit in our count. Looking at the state we are evaluating, 1010, we can see that the third bit from the right, Q2, is 0. The next state for the JK flip flop, while Q = 0, is determined by the input value J2. Looking at the J2 Karnaugh map at 1010, we can see that the state is not grouped in the minimization, therefore, J3 is a 0 and the state remains the same, 0. Q1 follows the same logic as Q3, the input is defined by K1 and the value at 1010 for the K1 Karnaugh map is not grouped, leading to the next state for Q1 to be 1.

Knowing the output for Q0, for state 1010, is 0, and the characteristics of the JK flip flop, the next state is determined by input J. Examining the Karnaugh map for J0, the don't care associated with state 1010 is grouped with the minimization, since a grouped don't care state becomes a 1, input J0 is 1.

Given the JK flip flops behavior, this means the next state of Q0 will be toggled, or, in this case, 1.

Finally, the next state is determined to be 1011, still an invalid state. However, there is hope yet of returning to a proper count sequence, if the next state for 1011 can lead to another invalid state or to a valid state directly, the system can recover from the error. To determine what the next state for 1011 is, we must do the above process again, this time evaluating for 1011.

Following this methodology for each of the invalid states, we come to the following results, given by our groupings of the Karnaugh maps used to create the input-forming logic.

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#### tshuck

Joined Oct 18, 2012
3,534

Not each invalid state progresses directly to a valid state. However, each invalid state does get to a valid state through a number of steps, meaning the system can, and will, eventually land itself into a valid state, given enough time. For this implementation, the system will only be in an invalid state for a a maximum of two clock cycles.

If, however, we were to determine that the system could not resolve an invalid state, given infinite clock cycles, we cannot guarantee the counter would operate as stated, namely as a Mod-10 counter. It may, or may not, operate correctly at start up.

Review
• A counter's modulus is the number of possible count values for a given implementation
• Don't care states in a Karnaugh always amount to a 1 or 0, depending on its grouping
• Using don't care states could result in a system lock up.

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#### tshuck

Joined Oct 18, 2012
3,534
Another person's opinion moved to the next page! 4...

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#### tshuck

Joined Oct 18, 2012
3,534
Images!!!!

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#### tshuck

Joined Oct 18, 2012
3,534
Images and other stuff I decide to attach! 9...4...

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#### MrChips

Joined Oct 2, 2009
21,664
Most flip-flops have both Q and Q'.
Why not use the Q' and eliminated the inverter?

#### tshuck

Joined Oct 18, 2012
3,534
Most flip-flops have both Q and Q'.
Why not use the Q' and eliminated the inverter?
I could say that I wanted to show another way of doing the design if Q' isn't present, but then I'd be half lying.

I have a tendency to leave them out due to practice. Most flip flops I use don't have the Q' output, so that just sort of stuck with me.

#### thatoneguy

Joined Feb 19, 2009
6,359
Add in applicable uses for such a construct.

A clock divider mod x, one pulse out per mod x in, for example.

This could allow people to understand the C % operator as well, if you want to tie it in.

Define it as "remainder after all divisions complete" or whatnot.

Just a suggestion, it may clutter the page, but not many free learning sites actually describe uses for one.

#### tshuck

Joined Oct 18, 2012
3,534
Add in applicable uses for such a construct.

A clock divider mod x, one pulse out per mod x in, for example.

This could allow people to understand the C % operator as well, if you want to tie it in.

Define it as "remainder after all divisions complete" or whatnot.

Just a suggestion, it may clutter the page, but not many free learning sites actually describe uses for one.
Actually I had a bit in there about how the modulus is the same idea as the C % operation, but took it out as I didn't think it fit, since most people wouldn't have an understanding of the concept of the modulo operator at the level that the modulo counter would be learned...

#### Georacer

Joined Nov 25, 2009
5,182
I think the following part is very confusing, especially the part in red:

From the Karnaugh maps we made earlier to determine our input-forming logic, we can determine our next state. Examine what happens to Q3 when the state is 1010 from the Karnaugh map. While in state 1010, Q3 is a 1, meaning K3 determines the next state.

Since we have not included the don't care state within the minimization grouping, it is treated as a 0, so the next state is unchanged from the current value: 1

Since it does not neccessarily return to a valid state, we must progress to Q2, which is 0 while the current count is 1010; the next state is determined by J2. Looking at the J2 Karnaugh map at 1010, we can see that the state is not grouped, therefore a 0 and the state remains the same, 0. The same is true for Q1, which remains in state1

Examining the Karnaugh map for Q0, however, has the don't care associated with state 1010 grouped with the minimization, counting it as a 1.

This means the next state of Q0 will be toggled, or, in this case, 1.
It involves insight on the procedure and visual inspection, traits not necessarily found in a novice.

I would prefer it, if the procedure was more formal:

• Choose an invalid state for inspection
• Apply the complete input logic to all of the FF states, in the form of Boolean formulas.
• Judge the results
Checking the MSBs first is a very logical thing to do, but not necessarily straightforward. Maybe worth mentioning, though.

#### tshuck

Joined Oct 18, 2012
3,534
I think the following part is very confusing, especially the part in red:

It involves insight on the procedure and visual inspection, traits not necessarily found in a novice.

I would prefer it, if the procedure was more formal:

• Choose an invalid state for inspection
• Apply the complete input logic to all of the FF states, in the form of Boolean formulas.
• Judge the results
Checking the MSBs first is a very logical thing to do, but not necessarily straightforward. Maybe worth mentioning, though.
This is a valid point. I suppose I made some choices without explaining my reasoning for making them.

I will have to rework it a bit, but that's the point of peer review, right?

#### Georacer

Joined Nov 25, 2009
5,182
Of course! I don't decide what goes in the e-book. However, I have the title of E-book developer too, so I guess my voice is somewhat more significant than a regular member. I think. I 'm not sure on what premises that rank was built.