I am trying to model a block and am writing behavioural verilog. I am using Icarus Verilog v0.9 to compile but i keep getting syntax error on line 43:
Any idea why this is? This seems like a legitimate line of code to me
Any idea why this is? This seems like a legitimate line of code to me
Rich (BB code):
`timescale 1ps/1ps
module unb_bfm (iUNB_ENABLE,
iREFCLK,
oDB_DATA,
oDB_CLK,
oDB_VALID);
input iUNB_ENABLE;
input iREFCLK;
output [1:0] oDB_DATA;
output oDB_CLK;
output oDB_VALID;
reg db_clk;
reg db_data_valid;
reg [1:0] db_data;
//wire m_value;
//wire n_value;
reg count_done;
reg count_m_done;
reg count_n_done;
reg db_clk_trigger;
reg db_data_trigger;
integer i;
parameter HALF_PERIOD = 667; // Approximately 750 MHz
parameter M_VALUE = 2;
parameter N_VALUE = 2;
initial begin
db_clk = 1'b0;
db_data_valid = 1'b0;
db_data = 2'b00;
count_done = 1'b0;
count_m_done = 1'b0;
count_n_done = 1'b0;
db_clk_trigger = 1'b0;
db_data_trigger = 1'b0;
end
while (iUNB_ENABLE==1) begin // <--------- this is line 43.
db_clk_trigger = 1'b1;
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