Desperate for help - Verilog

Thread Starter


Joined May 31, 2012
I am currently working on a published IEEE paper. Nothing fancy, I just want to replicate the result. I am having trouble even with that.
The paper is a Modified Montgomery Modular Multiplier. I follow the algorithm step by step clearly, but no matter what I am unable to achieve the desired result. What am I doing wrong?
Unfortunately, I am not able to find any ( or much ) literary work on this that could guide me. I plead you to go through and give me any advice possible. Thank you!

PS: The code is the Algorithm 4 found in the paper.




Joined Sep 25, 2013
This looks to be a process that finishes in 7 clocks ( 'i' in range [0:6]), but there are no non-blocking assignments in the code.
How do you know the result is wrong? A little more context for your question might help, as would maybe a different forum (say, here)
I have not much else to offer, you, though.


Joined Mar 31, 2012
It would be helpful if you were to format your code reasonably instead of having everything crammed against the left margin.