verilog code it has syntax error n no logical errror ...

plz compile this code in xilinx .....i am getting some errors not able to debug them plz help.....there is no logical errror ,,,,




module bus_enc(x_in, y_out);
input [7:0] x_in;
output [8:0] y_out;
output [8:0] out_prev;
wire [8:0] res;
wire res1;

initial
begin
out_prev=0;
end

assign res[8]=out_prev[8]^x_in[7];
assign res[7]=out_prev[7]^x_in[6];
assign res[6]=out_prev[6]^x_in[5];
assign res[5]=out_prev[5]^x_in[4];
assign res[4]=out_prev[4]^x_in[3];
assign res[3]=out_prev[3]^x_in[2];
assign res[2]=out_prev[2]^x_in[1];
assign res[1]=out_prev[1]^x_in[0];
assign res[0]=out_prev[0];

majority m1 (res,res1);
condition c1 (res1,x_in,y_out);
assign out_prev=y_out;
endmodule

module condition(ress,xn_in,out);
input ress;
input [7:0] xn_in;
output [8:0] out;
reg [8:0] out;
always@(ress,xn_in)
begin
if(ress==1)
begin
out[0]=1;
out[8:1]=~xn_in[7:0];

end
else
begin
out[0]=0;
out[8:1]=xn_in[7:0];

end
end
endmodule

module majority(xs_in,out);
input [8:0] xs_in;
output out;
wire s1,s2,s3,s4,s5,s6,s7,s8,c1,c2,c3,c4,c5;
full_adder f1 (xs_in[8],xs_in[7],xs_in[6],s1,c1);
full_adder f2 (xs_in[5],xs_in[4],xs_in[3],s2,c2);
full_adder f3 (xs_in[2],xs_in[1],xs_in[0],s3,c3);
full_adder f4 (s1,s2,s3,s4,c4);
full_adder f5 (c1,c2,c3,s5,c5);
assign s6=s4&s5&c4;
assign s7=s4|s5|c4;
assign s8=s7&c5;
assign out=s6|s8;
endmodule

module full_adder(a,b,c,s,cout);
input a,b,c;
output s,cout;
assign s=a^b^c;
assign cout=(a&b)|(b&c)|(c&a);
endmodule